{"title":"多媒体视频应用中使用插值滤波器的高分辨率图像缩放器","authors":"Hwang, Sunwoo, Kang, Gerard","doi":"10.1109/30.628720","DOIUrl":null,"url":null,"abstract":"This paper proposes a high-performance down scaler to improve the quality of a down-scaled image using interpolation filter. It uses a non-linear phase property of the digital filter to reduce hardware complexity. The implemented architecture is composed of four blocks: (i) line memory, (ii) vertical scaler with interpolation filter, (iii) horizontal scaler with interpolation filter, and (iv) FIFO. It has been fabricated by using 0.65 /spl mu/m CMOS process.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"High Resolution Image Scaler Using Interpolation Filter For Multimedia Video Applications\",\"authors\":\"Hwang, Sunwoo, Kang, Gerard\",\"doi\":\"10.1109/30.628720\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a high-performance down scaler to improve the quality of a down-scaled image using interpolation filter. It uses a non-linear phase property of the digital filter to reduce hardware complexity. The implemented architecture is composed of four blocks: (i) line memory, (ii) vertical scaler with interpolation filter, (iii) horizontal scaler with interpolation filter, and (iv) FIFO. It has been fabricated by using 0.65 /spl mu/m CMOS process.\",\"PeriodicalId\":127085,\"journal\":{\"name\":\"1997 International Conference on Consumer Electronics\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/30.628720\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/30.628720","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
摘要
本文提出了一种高性能的降尺度器，利用插值滤波来提高降尺度图像的质量。它利用数字滤波器的非线性相位特性来降低硬件复杂度。实现的架构由四个块组成:(i)行存储器，(ii)带插值滤波器的垂直缩放器，(iii)带插值滤波器的水平缩放器，以及(iv) FIFO。采用0.65 /spl μ m CMOS工艺制备。
High Resolution Image Scaler Using Interpolation Filter For Multimedia Video Applications
This paper proposes a high-performance down scaler to improve the quality of a down-scaled image using interpolation filter. It uses a non-linear phase property of the digital filter to reduce hardware complexity. The implemented architecture is composed of four blocks: (i) line memory, (ii) vertical scaler with interpolation filter, (iii) horizontal scaler with interpolation filter, and (iv) FIFO. It has been fabricated by using 0.65 /spl mu/m CMOS process.
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