在高电阻硅衬底的SOI层中集成cmos电子器件

IEEE Conference on Nuclear Science Symposium and Medical Imaging Pub Date : 1992-10-25 DOI:10.1109/NSSMIC.1992.301276

B. Dierickx, A. Alaerts, I. Debusschere, E. Simoen, J. Vlummens, C. Claeys, H. Maes, L. Hermans, E. Heijne, P. Jarron, F. Anghinolfi, P. Aspell, Marnie L Campbell, F. Pengg, L. Bosisio, E. Focardi, P. Delpierre, A. Mekkaoui, M. Habrard, D. Sauvage

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引用次数: 2

摘要

报道了电子器件与高阻硅探测器的单片集成。该方法基于CMOS电路集成在高电阻率SOI(绝缘体上硅)晶圆的顶层。在初步的可行性研究中，高电阻率晶圆采用SOI层制造方法，并通过简单的二极管工艺评估了两个主要特性:二极管泄漏和可能的掺杂浓度增加。在项目的第二阶段，执行了一个完整的SOI-on-H Omega流程。然后评估MOSFET的行为。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Integration of CMOS-electronics in an SOI layer on high-resistivity silicon substrates

The monolithic integration of electronics and high-resistivity silicon detectors is reported. The approach is based on CMOS circuit integration in the top layer of high-resistivity SOI (silicon-on-insulator) wafers. In a preliminary feasibility study, high-resistivity wafers were subjected to SOI layer fabrication methods and evaluated with a simple diode process for two main characteristics: diode leakage and possible dopant concentration increase. In the second phase of the project, a full SOI-on-H Omega process was executed. MOSFET behavior was then evaluated.<>

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IEEE Conference on Nuclear Science Symposium and Medical Imaging

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