{"title":"DCT触发率作为抗混叠贝塞尔滤波器环境变化的函数","authors":"Z. Szadkowski, A. Szadkowska","doi":"10.1109/ICM.2017.8268810","DOIUrl":null,"url":null,"abstract":"The standard triggers T1 and ToT for the surface detectors of the Pierre Auger Observatory based on 3-fold (T1) or 2-fold (ToT) coincidences in the time domain. The Discrete Cosine Transform (DCT) algorithm implemented as 3 engines for 3 PMT channels implemented into the surface detector Front-End Board (FEB) FPGA analyzes online shapes of the signal waveforms (ADC traces) and generates a trigger if selected number (7–9) of sub-triggers (as scaled DCT[k]/DCT[1]) are “fired” in at least two channels simultaneously. For assumed sampling frequency fS = 120 MHz, the filter is built from RLC components on relatively small values. Resistors and inductors are available in 0.1 % and 5 % tolerance, however, capacitors in pF range are available even in 0.1 pF, but the parasitic capacitance on the FEB can dramatically change the frequency characteristics. Daily temperature variations reach even 40 ° C, which additionally change the characteristic of the analog FEB section. The paper analyzes the influence of the Bessel filter frequency characteristics on the efficiency of the DCT trigger.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"DCT trigger rate as a function of anti-aliasing Bessel filter environmental variation\",\"authors\":\"Z. Szadkowski, A. Szadkowska\",\"doi\":\"10.1109/ICM.2017.8268810\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The standard triggers T1 and ToT for the surface detectors of the Pierre Auger Observatory based on 3-fold (T1) or 2-fold (ToT) coincidences in the time domain. The Discrete Cosine Transform (DCT) algorithm implemented as 3 engines for 3 PMT channels implemented into the surface detector Front-End Board (FEB) FPGA analyzes online shapes of the signal waveforms (ADC traces) and generates a trigger if selected number (7–9) of sub-triggers (as scaled DCT[k]/DCT[1]) are “fired” in at least two channels simultaneously. For assumed sampling frequency fS = 120 MHz, the filter is built from RLC components on relatively small values. Resistors and inductors are available in 0.1 % and 5 % tolerance, however, capacitors in pF range are available even in 0.1 pF, but the parasitic capacitance on the FEB can dramatically change the frequency characteristics. Daily temperature variations reach even 40 ° C, which additionally change the characteristic of the analog FEB section. The paper analyzes the influence of the Bessel filter frequency characteristics on the efficiency of the DCT trigger.\",\"PeriodicalId\":115975,\"journal\":{\"name\":\"2017 29th International Conference on Microelectronics (ICM)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 29th International Conference on Microelectronics (ICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2017.8268810\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 29th International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2017.8268810","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
DCT trigger rate as a function of anti-aliasing Bessel filter environmental variation
The standard triggers T1 and ToT for the surface detectors of the Pierre Auger Observatory based on 3-fold (T1) or 2-fold (ToT) coincidences in the time domain. The Discrete Cosine Transform (DCT) algorithm implemented as 3 engines for 3 PMT channels implemented into the surface detector Front-End Board (FEB) FPGA analyzes online shapes of the signal waveforms (ADC traces) and generates a trigger if selected number (7–9) of sub-triggers (as scaled DCT[k]/DCT[1]) are “fired” in at least two channels simultaneously. For assumed sampling frequency fS = 120 MHz, the filter is built from RLC components on relatively small values. Resistors and inductors are available in 0.1 % and 5 % tolerance, however, capacitors in pF range are available even in 0.1 pF, but the parasitic capacitance on the FEB can dramatically change the frequency characteristics. Daily temperature variations reach even 40 ° C, which additionally change the characteristic of the analog FEB section. The paper analyzes the influence of the Bessel filter frequency characteristics on the efficiency of the DCT trigger.