锁相环电路的宽工作范围采集技术

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824098

Yi-Cheng Chang, E.W. Greeneich

{"title":"锁相环电路的宽工作范围采集技术","authors":"Yi-Cheng Chang, E.W. Greeneich","doi":"10.1109/APASIC.1999.824098","DOIUrl":null,"url":null,"abstract":"A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 /spl mu/m CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Wide operating-range acquisition technique for PLL circuits\",\"authors\":\"Yi-Cheng Chang, E.W. Greeneich\",\"doi\":\"10.1109/APASIC.1999.824098\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 /spl mu/m CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"112 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824098\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824098","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

设计了一种采用粗转向技术的宽范围锁相环(PLL)电路，并在MOSIS 1.2 /spl mu/m CMOS技术中实现。整个锁相环电路已经进行了仿真，并且可以在HSPICE上使用3伏电源在160-440 MHz的频率范围内获得锁定。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Wide operating-range acquisition technique for PLL circuits

A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 /spl mu/m CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

自引率

0.00%

发文量