From interpreted Petri net specification to reprogrammable logic controller design

The goal of this paper is to present the design methodology for the modelling and synthesis of discrete event controllers for compact, fast and reliable embedded systems, using related Petri net theory, rule-based system theory (conditional mathematical logic), and hardware description languages (VHDL, Verilog). The well structured specification, which is represented in the human readable logic language, has a direct impact on the validation, formal verification and implementation of application specific logic controllers (ASLC) mapped into reconfigurable logic devices (FPGA). Reprogrammable logic controllers (RLC) may replace traditional PLCs in many industrial applications.