工程单NMOS和PMOS输出缓冲器的最大失效电压在先进的CMOS技术

2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI:10.1109/EOSESD.2004.5272600

M. Khazhinsky, J. Miller, M. Stockinger, J. Weldon

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引用次数: 25

摘要

在本文中，我们提出了新的电路设计选项，以提高NMOS和PMOS输出缓冲晶体管的ldco有效失效电压(Vt2)，从而有助于保护这些脆弱的器件。通过实验数据、器件和电路模拟，我们演示了如何为缓冲门或二次ESD二极管放置串联电阻和偏置电路可以显着增加Vt2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies

In this paper we propose new circuit design options for increasing the ldquoeffectiverdquo failure voltage (Vt2) of both NMOS and PMOS output buffer transistors, thereby helping to protect these fragile devices. Using experimental data, device and circuit simulations we demonstrate how placing a series resistor and either a bias circuit for the buffer gates or secondary ESD diodes may significantly increase Vt2.

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2004 Electrical Overstress/Electrostatic Discharge Symposium

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