Wen-jie Jiang, Ming-zhu Zhou, G. Su, Jun Liu, Rui Lin, Yong-ming Liang
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A design of frequency doubler based on 0.5um lnP HBT process
This paper presents a type of frequency doubler with a single transistor designed with 0.5 um lnP HBT process. The frequency doubler employs LC circuit to achieve input and output impedance matching. At the emitter of the transistor, a λ/4@2f0 transmission line is connected to increase the output power. The input power of the frequency doubler is 5 dBm. In the output frequency range of 50 ∼ 86 GHz, the small signal gain S21 is stabilized at −5.2 dB, the fundamental suppression is greater than 13 dBc, and the total area of the layout is 0.265 mm2. The power supply voltage of the frequency doubler is 3 V and the DC power consumption is 6.27 mW.
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