IEEE 1284软核实现问题

Myoung-Han Lee, Sun-Kyu Kim, Myoung-Sun Park, Yl-Seong Bae, P. Chung
{"title":"IEEE 1284软核实现问题","authors":"Myoung-Han Lee, Sun-Kyu Kim, Myoung-Sun Park, Yl-Seong Bae, P. Chung","doi":"10.1109/APASIC.1999.824080","DOIUrl":null,"url":null,"abstract":"In this paper, we present a re-usable softcore for the IEEE 1284 protocol for parallel data transmission. It consists of two parts. One is the firmware to cope with the IEEE-1284 protocol being executed in the processor and the other is the hardware engine to accelerate the basic communication mechanism. Using our evaluation system, it is verified that the designed core is fully compliant with the specification. Additionally, we show the results on the performance comparison between the compatibility and ECP modes of the IEEE-1284 standard.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"IEEE 1284 softcore-implementation issues\",\"authors\":\"Myoung-Han Lee, Sun-Kyu Kim, Myoung-Sun Park, Yl-Seong Bae, P. Chung\",\"doi\":\"10.1109/APASIC.1999.824080\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a re-usable softcore for the IEEE 1284 protocol for parallel data transmission. It consists of two parts. One is the firmware to cope with the IEEE-1284 protocol being executed in the processor and the other is the hardware engine to accelerate the basic communication mechanism. Using our evaluation system, it is verified that the designed core is fully compliant with the specification. Additionally, we show the results on the performance comparison between the compatibility and ECP modes of the IEEE-1284 standard.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824080\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824080","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

在本文中,我们提出了一个可重用的软件核,用于并行数据传输的ieee1284协议。它由两部分组成。一个是固件,用于处理处理器中正在执行的IEEE-1284协议;另一个是硬件引擎,用于加速基本通信机制。使用我们的评估系统,验证了设计的核心完全符合规范。此外,我们还展示了IEEE-1284标准的兼容模式和ECP模式的性能比较结果。
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IEEE 1284 softcore-implementation issues
In this paper, we present a re-usable softcore for the IEEE 1284 protocol for parallel data transmission. It consists of two parts. One is the firmware to cope with the IEEE-1284 protocol being executed in the processor and the other is the hardware engine to accelerate the basic communication mechanism. Using our evaluation system, it is verified that the designed core is fully compliant with the specification. Additionally, we show the results on the performance comparison between the compatibility and ECP modes of the IEEE-1284 standard.
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