M. Jo, C. Kang, K. Ang, J. Huang, P. Kirsch, R. Jammy
{"title":"了解和改进全栅末级高k/金属栅nmosfet在TDDB应力下的SILC行为","authors":"M. Jo, C. Kang, K. Ang, J. Huang, P. Kirsch, R. Jammy","doi":"10.1109/VLSI-TSA.2012.6210154","DOIUrl":null,"url":null,"abstract":"Stress-induced leakage current (SILC) behavior in full gate-last (FGL) high-k/metal gate devices was evaluated and compared to gate-first (GF) devices. To improve SILC characteristics, Zr was introduced into the high-k bulk region. Incorporating Zr can reduce SILC in both FGL and GF devices by suppressing trap generation in the high-k bulk region under time-dependent dielectric breakdown (TDDB) stress. However, the interfacial layer quality can be a critical SILC issue in FGL devices.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Understanding and improving SILC behavior under TDDB stress in full gate-last high-k/metal gate nMOSFETs\",\"authors\":\"M. Jo, C. Kang, K. Ang, J. Huang, P. Kirsch, R. Jammy\",\"doi\":\"10.1109/VLSI-TSA.2012.6210154\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Stress-induced leakage current (SILC) behavior in full gate-last (FGL) high-k/metal gate devices was evaluated and compared to gate-first (GF) devices. To improve SILC characteristics, Zr was introduced into the high-k bulk region. Incorporating Zr can reduce SILC in both FGL and GF devices by suppressing trap generation in the high-k bulk region under time-dependent dielectric breakdown (TDDB) stress. However, the interfacial layer quality can be a critical SILC issue in FGL devices.\",\"PeriodicalId\":388574,\"journal\":{\"name\":\"Proceedings of Technical Program of 2012 VLSI Technology, System and Application\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Technical Program of 2012 VLSI Technology, System and Application\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-TSA.2012.6210154\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2012.6210154","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Understanding and improving SILC behavior under TDDB stress in full gate-last high-k/metal gate nMOSFETs
Stress-induced leakage current (SILC) behavior in full gate-last (FGL) high-k/metal gate devices was evaluated and compared to gate-first (GF) devices. To improve SILC characteristics, Zr was introduced into the high-k bulk region. Incorporating Zr can reduce SILC in both FGL and GF devices by suppressing trap generation in the high-k bulk region under time-dependent dielectric breakdown (TDDB) stress. However, the interfacial layer quality can be a critical SILC issue in FGL devices.
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