一种浮点融合加减运算单元

2008 51st Midwest Symposium on Circuits and Systems Pub Date : 2008-12-05 DOI:10.1109/MWSCAS.2008.4616850

H. Saleh, E. Swartzlander

{"title":"一种浮点融合加减运算单元","authors":"H. Saleh, E. Swartzlander","doi":"10.1109/MWSCAS.2008.4616850","DOIUrl":null,"url":null,"abstract":"A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45 nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"66","resultStr":"{\"title\":\"A floating-point fused add-subtract unit\",\"authors\":\"H. Saleh, E. Swartzlander\",\"doi\":\"10.1109/MWSCAS.2008.4616850\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45 nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.\",\"PeriodicalId\":118637,\"journal\":{\"name\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"66\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2008.4616850\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 51st Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2008.4616850","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 66

摘要

描述了一种浮点融合加减单元，该单元对一对普通的单精度数据同时执行浮点加减操作，所用时间与使用传统浮点加法器执行一次加法所花费的时间大致相同。当在45纳米工艺中放置和布线时，融合的加减单元仅比传统的浮点加法器大40%左右。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A floating-point fused add-subtract unit

A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45 nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2008 51st Midwest Symposium on Circuits and Systems

自引率

0.00%

发文量