{"title":"基板隔离选项对高压闭锁的影响","authors":"D. Marreiro, V. Vashchenko","doi":"10.23919/EOS/ESD.2018.8509741","DOIUrl":null,"url":null,"abstract":"The novel wafer-level test method is used to study HV latch-up specifics through comparisons between two most common power analog processes - Extended CMOS and BCD. The dependence of the critical injector-victim voltage upon the injector-victim spacing is analyzed toward practically useful high-and low-side injection HV latch-up regularities.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Substrate Isolation Options Effect on HV Latch-up\",\"authors\":\"D. Marreiro, V. Vashchenko\",\"doi\":\"10.23919/EOS/ESD.2018.8509741\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The novel wafer-level test method is used to study HV latch-up specifics through comparisons between two most common power analog processes - Extended CMOS and BCD. The dependence of the critical injector-victim voltage upon the injector-victim spacing is analyzed toward practically useful high-and low-side injection HV latch-up regularities.\",\"PeriodicalId\":328499,\"journal\":{\"name\":\"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"volume\":\"91 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/EOS/ESD.2018.8509741\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EOS/ESD.2018.8509741","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The novel wafer-level test method is used to study HV latch-up specifics through comparisons between two most common power analog processes - Extended CMOS and BCD. The dependence of the critical injector-victim voltage upon the injector-victim spacing is analyzed toward practically useful high-and low-side injection HV latch-up regularities.
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