Dynamic Dielectric Protection For I/0 Circuits Fabricated In A 2.5V CMOS Technology Interfacing To A 3.3V LVTTL Bus

Introduction As gate oxide thickness is reduced in advanced low-voltage CMOS technologies, protecting the Ti0 circuits’ dielectrics from over-voltage conditions becomes necessary when interfacing to higher voltage buses [1]. 3.3V LVTTL compatible I/O circuits fabricated in a 2.5V CMOS technology are presented. Dynamic dielectric protection techniques are employed to prevent overstressing gate oxide in U 0 circuits of a 4Mb SRAM where undershootlovershoot peaks of -lVi 4.3V can occur before diode clamping begins [2].