ASIC Implementation of Energy-Optimized Successive Cancellation Polar Decoders for Internet of Things

In this paper, a low-energy rate 1/2 successive cancellation (SC) decoder hardware architecture is proposed for Internet of Things (IoT) applications. Arikan’s SC decoder and different optimized versions of it are implemented in ASIC flow. Hardware optimizations are applied to the conventional SC architecture, including the removal of frozen bits driving blocks, resource sharing between f and g blocks and the removal of log-likelihood magnitude computation in the last stage. Synthesis results show that these optimizations provide 38.7% saving in energy/bit consumption, 83% saving in area and 68.0% increase in throughput for 64-bit conventional SC decoder and up to 79.5% in 1024-bit implementation. The synthesis results are compared with the literature, and the results show that the proposed 64-bit SC architecture gives less energy/bit consumption and area. Moreover, linearly scaled 1024-bit synthesis results predict a middle-ground performance of the proposed architecture compared to the literature, hence suggesting the proposed structure to IoT applications, especially small packet size applications.