Shouping Li, Yang Guo, Yao Liu, Jianjun Chen, Qing Xu, Jizuo Zhang
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A 1.2V 12 Bits SAR ADC with a Two Stages Amplifier Full-scale Differential Dynamic Comparator
This paper put forward a 12-b 25MS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) architecture based on power efficiency Capacitive Digital-to-Analog (CDAC) and a two stages amplifier full-scale differential dynamic comparator. A tri-level switching scheme is being used to achieve the highest switching efficiency while still conserving the symmetry in error tolerance. The prototype implementation in 130nm CMOS technology achieves a 70.1dB SNDR at 25MS/s, while dissipating 0.21mW from a 1.2V voltage supply, leading to a FoM of 37.4fJ/conversion-step.
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