A 0.1/spl mu/A standby current, bouncing-noise-immune 1Mb SRAM

I) Introduction Recentlv. lhlb SRAMs with nolvsilicon load resistor cell have been r e p ~ r t e d l , ~ , ~ , ~ . But i t becomes difficult to reduce standby current less than ILIA, because of data retention problem and process difficulty of high resistivity polysilicon formation. This paper describes a 1Mb SRAM with a standby current of O.IpA, employing, as cell load devices, p-channel polysilicon transistors with offset gate-drain structure, stacked on n-channel driver transistors5. The SRAM also employed an optimal sensitivity-control scheme of clock generators, immune to VCCIGND voltagebouncing noises which induce serious problem in a byte-wide RAM with an address transition, det,ector. The circuit scheme widened input voltage margins by 0.2V.