{"title":"论偏压相关电荷注入对AMS电路中SET评估的重要性","authors":"Valentín Gutiérrez, G. Léger","doi":"10.1109/newcas49341.2020.9159811","DOIUrl":null,"url":null,"abstract":"Single Event Transients have become a serious issue in safety-critical applications of Analog and Mixed-Signal (AMS) circuits. Therefore, an evaluation must be carried out in order to diagnose the critical nodes but also to get an idea of the global sensitivity of the circuit, as a proxy to its experimental cross-section. In this work we evaluate two different top-down approaches considering or not the biasing of the impacted transistor to compute the injected charge. Performing an exhaustive evaluation campaign on a high performance buffer as a case of study, it will be shown that the error committed by the charge difference is greater than the one committed by simulating with the simple schematic without layout parasitics. However, the correlation between both approaches is high, so the critical nodes appear in the same order.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"On the importance of bias-dependent charge injection for SET evaluation in AMS Circuits\",\"authors\":\"Valentín Gutiérrez, G. Léger\",\"doi\":\"10.1109/newcas49341.2020.9159811\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Single Event Transients have become a serious issue in safety-critical applications of Analog and Mixed-Signal (AMS) circuits. Therefore, an evaluation must be carried out in order to diagnose the critical nodes but also to get an idea of the global sensitivity of the circuit, as a proxy to its experimental cross-section. In this work we evaluate two different top-down approaches considering or not the biasing of the impacted transistor to compute the injected charge. Performing an exhaustive evaluation campaign on a high performance buffer as a case of study, it will be shown that the error committed by the charge difference is greater than the one committed by simulating with the simple schematic without layout parasitics. However, the correlation between both approaches is high, so the critical nodes appear in the same order.\",\"PeriodicalId\":135163,\"journal\":{\"name\":\"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/newcas49341.2020.9159811\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/newcas49341.2020.9159811","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On the importance of bias-dependent charge injection for SET evaluation in AMS Circuits
Single Event Transients have become a serious issue in safety-critical applications of Analog and Mixed-Signal (AMS) circuits. Therefore, an evaluation must be carried out in order to diagnose the critical nodes but also to get an idea of the global sensitivity of the circuit, as a proxy to its experimental cross-section. In this work we evaluate two different top-down approaches considering or not the biasing of the impacted transistor to compute the injected charge. Performing an exhaustive evaluation campaign on a high performance buffer as a case of study, it will be shown that the error committed by the charge difference is greater than the one committed by simulating with the simple schematic without layout parasitics. However, the correlation between both approaches is high, so the critical nodes appear in the same order.