{"title":"一种基于平衡降噪技术的CMOS宽带低噪声放大器","authors":"Youchun Liao, Zhangwen Tang, Hao Min","doi":"10.1109/ASSCC.2007.4425739","DOIUrl":null,"url":null,"abstract":"A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"A CMOS wide-band low-noise amplifier with balun-based noise-canceling technique\",\"authors\":\"Youchun Liao, Zhangwen Tang, Hao Min\",\"doi\":\"10.1109/ASSCC.2007.4425739\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.\",\"PeriodicalId\":186095,\"journal\":{\"name\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2007.4425739\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425739","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34
摘要
提出了一种基于电容交叉耦合拓扑结构的差分高线性低噪声放大器。片外平衡器用于提供直流偏置和消除跨导MOS晶体管的通道热噪声。LNA采用NMOS负载,并提供额外的信号前馈和消噪路径。分析表明,跨导MOST的噪声贡献仅为gamma/20,所提LNA的噪声系数(NF)为1 + 0.2gamma。该芯片采用0.18 μ m MMRF CMOS工艺实现。测量结果表明,在50 m - 860mhz频率范围内,LNA可实现15 dB增益,2.5 dB NF, 8.3 dBm IIP3,并且仅消耗来自1.8 v电源的4 mA电流。
A CMOS wide-band low-noise amplifier with balun-based noise-canceling technique
A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.