采用20nm CMOS的36 Gbps 16.9 mW/Gbps收发器,具有1分接DFE和四分之一速率时钟分布

T. Hashida, Y. Tomita, Yuuki Ogata, Kosuke Suzuki, S. Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, A. Konmoto, Yoshitomo Ozeki, H. Adachi, H. Yamaguchi, Y. Koyanagi, H. Tamura
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引用次数: 2

摘要

介绍了一种具有连续时间线性均衡器和20nm CMOS 1抽头DFE的36gbps收发器。收发器使用四分之一速率(即9 ghz)差时钟分布来降低时钟传输功率。驱动收发器前端的多相半速率时钟信号由延迟锁定环路和倍频器产生,系统地减少了倾斜和抖动的影响。收发器占地0.55 mm2,在0.9 v电源下消耗609.9 mW的功率。
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A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution
A 36-Gbps transceiver with a continuous-time linear equalizer and a 1-tap DFE in 20-nm CMOS is demonstrated. The transceiver uses a quarter-rate (i.e., 9-GHz) differential-clock distribution to reduce the clock-delivery power. Multi-phase half-rate clock signals that drive the transceiver front-ends are generated by a delay-locked loop and frequency doublers that systematically reduce the impact of skew and jitter. The transceiver occupies 0.55 mm2 and consumes 609.9 mW of power from a 0.9-V supply.
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