{"title":"FPGA外设接口的嵌入驱动","authors":"S. Bhandari, S. Pujari, S. Subbaraman","doi":"10.1109/ICETET.2008.205","DOIUrl":null,"url":null,"abstract":"The paper covers a simple RTL implementation of a command processor with its associated macroinstructions implemented on FPGA device to drive an external peripherals having processor like bus interface. Soft processor is used inside FPGA device to handle the tasks of software driver for peripheral controller. The paper discusses an approach to mimic a simple soft processor to handle the task at core layer of driver for basic communication with peripherals connected to FPGA. The present architecture envisages a three-tier implementation of peripheral hardware software co-design interface. The Top level is an application processor connected to FPGA for handling high-level application layers. The application processor could be a generic processor or a DSP. The next second level is a soft processor embedded in FPGA for handling middle layer software. Command processor or pre-processor handles the third bottom core layer task/command specific processing.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Embedding Driver for a Peripheral Interface on FPGA\",\"authors\":\"S. Bhandari, S. Pujari, S. Subbaraman\",\"doi\":\"10.1109/ICETET.2008.205\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper covers a simple RTL implementation of a command processor with its associated macroinstructions implemented on FPGA device to drive an external peripherals having processor like bus interface. Soft processor is used inside FPGA device to handle the tasks of software driver for peripheral controller. The paper discusses an approach to mimic a simple soft processor to handle the task at core layer of driver for basic communication with peripherals connected to FPGA. The present architecture envisages a three-tier implementation of peripheral hardware software co-design interface. The Top level is an application processor connected to FPGA for handling high-level application layers. The application processor could be a generic processor or a DSP. The next second level is a soft processor embedded in FPGA for handling middle layer software. Command processor or pre-processor handles the third bottom core layer task/command specific processing.\",\"PeriodicalId\":269929,\"journal\":{\"name\":\"2008 First International Conference on Emerging Trends in Engineering and Technology\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 First International Conference on Emerging Trends in Engineering and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICETET.2008.205\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 First International Conference on Emerging Trends in Engineering and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICETET.2008.205","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Embedding Driver for a Peripheral Interface on FPGA
The paper covers a simple RTL implementation of a command processor with its associated macroinstructions implemented on FPGA device to drive an external peripherals having processor like bus interface. Soft processor is used inside FPGA device to handle the tasks of software driver for peripheral controller. The paper discusses an approach to mimic a simple soft processor to handle the task at core layer of driver for basic communication with peripherals connected to FPGA. The present architecture envisages a three-tier implementation of peripheral hardware software co-design interface. The Top level is an application processor connected to FPGA for handling high-level application layers. The application processor could be a generic processor or a DSP. The next second level is a soft processor embedded in FPGA for handling middle layer software. Command processor or pre-processor handles the third bottom core layer task/command specific processing.