一种用于65nm片上互连的低摆幅信号电路技术

2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI:10.1109/SOCC.2006.283900

V. Venkatraman, M. Anders, Himanshu Kaul, W. Burleson, R. Krishnamurthy

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引用次数: 14

摘要

本文介绍了一种低摆幅片上互连信号技术。与在中间和全局互连上的传统中继器相比，一个简单的接收器电路可以显著降低总能量和延迟。采用1.1V电源的65nm CMOS技术的5 mm最小间距全球互连显示总能量减少56%，延迟减少21%，面积减少86%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects

This paper describes a low-swing on-chip interconnect signaling technique. A simple receiver circuit enables significant total energy and delay reduction compared to conventional repeaters over intermediate and global interconnects. A 5 mm minimum pitch global interconnect in 65nm CMOS technology using 1.1V supply exhibits a reduction of 56% in total energy, 21% in delay, and 86% in area.

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2006 IEEE International SOC Conference

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