{"title":"光子中介器的高能效数据速率","authors":"N. Chujo, Y. Uematsu, M. Yasunaga","doi":"10.1109/ICSJ.2014.7009600","DOIUrl":null,"url":null,"abstract":"We describe a chip-to-chip interconnect solution that will enable 40-Tb/s bandwidth per apparatus and 10-Tb/s bandwidth per LSI in 2020. By using an interposer which can increase wiring density, we aim to increase the parallel number of data, relax the data rate, and integrate optical transceivers in the package. Doing so both enhances bandwidth and reduces power consumption. By analyzing the optical interconnect composed of a Si interposer, VCSEL, and PD, we determine that about 10Gb/s is the most power efficient data rate.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Power efficient data rate for photonic interposer\",\"authors\":\"N. Chujo, Y. Uematsu, M. Yasunaga\",\"doi\":\"10.1109/ICSJ.2014.7009600\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe a chip-to-chip interconnect solution that will enable 40-Tb/s bandwidth per apparatus and 10-Tb/s bandwidth per LSI in 2020. By using an interposer which can increase wiring density, we aim to increase the parallel number of data, relax the data rate, and integrate optical transceivers in the package. Doing so both enhances bandwidth and reduces power consumption. By analyzing the optical interconnect composed of a Si interposer, VCSEL, and PD, we determine that about 10Gb/s is the most power efficient data rate.\",\"PeriodicalId\":362502,\"journal\":{\"name\":\"IEEE CPMT Symposium Japan 2014\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE CPMT Symposium Japan 2014\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSJ.2014.7009600\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE CPMT Symposium Japan 2014","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSJ.2014.7009600","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We describe a chip-to-chip interconnect solution that will enable 40-Tb/s bandwidth per apparatus and 10-Tb/s bandwidth per LSI in 2020. By using an interposer which can increase wiring density, we aim to increase the parallel number of data, relax the data rate, and integrate optical transceivers in the package. Doing so both enhances bandwidth and reduces power consumption. By analyzing the optical interconnect composed of a Si interposer, VCSEL, and PD, we determine that about 10Gb/s is the most power efficient data rate.
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