N. Prokopenko, N. Butyrlagin, A. Serebryakov, I. Pakhomov
{"title":"超快adc的输入模拟部分","authors":"N. Prokopenko, N. Butyrlagin, A. Serebryakov, I. Pakhomov","doi":"10.1109/EWDTS.2014.7027051","DOIUrl":null,"url":null,"abstract":"The modified method of the increase of the response speed of flash ADCs with the differential input which renders possible to reduce the effect of the parasitic capacitances of active and passive components of the analog sections and also to optimize their gain flatness is reviewed. The additional emitter follower and balancing capacitor are fed into each analog section to extend the bandwidth of ADC up to 50 GH.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"267 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The input analog section of the ultrafast ADCs\",\"authors\":\"N. Prokopenko, N. Butyrlagin, A. Serebryakov, I. Pakhomov\",\"doi\":\"10.1109/EWDTS.2014.7027051\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The modified method of the increase of the response speed of flash ADCs with the differential input which renders possible to reduce the effect of the parasitic capacitances of active and passive components of the analog sections and also to optimize their gain flatness is reviewed. The additional emitter follower and balancing capacitor are fed into each analog section to extend the bandwidth of ADC up to 50 GH.\",\"PeriodicalId\":272780,\"journal\":{\"name\":\"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)\",\"volume\":\"267 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2014.7027051\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2014.7027051","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The modified method of the increase of the response speed of flash ADCs with the differential input which renders possible to reduce the effect of the parasitic capacitances of active and passive components of the analog sections and also to optimize their gain flatness is reviewed. The additional emitter follower and balancing capacitor are fed into each analog section to extend the bandwidth of ADC up to 50 GH.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
