{"title":"深亚微米超大规模集成电路中多价值技术的挑战","authors":"T. Hanyu","doi":"10.1109/ISMVL.2001.924579","DOIUrl":null,"url":null,"abstract":"A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass-transistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Challenge of a multiple-valued technology in recent deep-submicron VLSI\",\"authors\":\"T. Hanyu\",\"doi\":\"10.1109/ISMVL.2001.924579\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass-transistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.\",\"PeriodicalId\":297353,\"journal\":{\"name\":\"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2001.924579\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2001.924579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Challenge of a multiple-valued technology in recent deep-submicron VLSI
A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass-transistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.