{"title":"无线视频对讲视频解码MPSoC的设计","authors":"Jing Zhang, Duoli Zhang, Gaoming Du","doi":"10.1109/ICASID.2010.5551827","DOIUrl":null,"url":null,"abstract":"Wireless video interphone cannot only provide portability, but also connect people through video communication, so it gains more and more interest in consumer electronics. To design such systems, it needs high performance video processing engine. In this paper, a Multi-processor system on a chip (MPSoC) is designed, in which there are one 32-bit RISC CPU and a low power, high performance H.264 codec. The RISC CPU controls the system operation, and the H.264 codec is responsible for video decoding. Due to the large number of data to be processed, an off-chip DDRII SDRAM is used to store source stream and intermediate data. Additionally, the MPSoC can receive real-time wireless video and convert the decoded data into RGB data format that can be displayed on LCD. The MPSoC is implemented on EP3C120F780C8N FPGA, and takes up 71% resource of the total device resource. Experiment results show that it runs 32MHz, and can perform real-time video decoding, with the frame rate up to 30fps.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of video decoding MPSoC for wireless video intercom\",\"authors\":\"Jing Zhang, Duoli Zhang, Gaoming Du\",\"doi\":\"10.1109/ICASID.2010.5551827\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Wireless video interphone cannot only provide portability, but also connect people through video communication, so it gains more and more interest in consumer electronics. To design such systems, it needs high performance video processing engine. In this paper, a Multi-processor system on a chip (MPSoC) is designed, in which there are one 32-bit RISC CPU and a low power, high performance H.264 codec. The RISC CPU controls the system operation, and the H.264 codec is responsible for video decoding. Due to the large number of data to be processed, an off-chip DDRII SDRAM is used to store source stream and intermediate data. Additionally, the MPSoC can receive real-time wireless video and convert the decoded data into RGB data format that can be displayed on LCD. The MPSoC is implemented on EP3C120F780C8N FPGA, and takes up 71% resource of the total device resource. Experiment results show that it runs 32MHz, and can perform real-time video decoding, with the frame rate up to 30fps.\",\"PeriodicalId\":391931,\"journal\":{\"name\":\"2010 International Conference on Anti-Counterfeiting, Security and Identification\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Anti-Counterfeiting, Security and Identification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASID.2010.5551827\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Anti-Counterfeiting, Security and Identification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASID.2010.5551827","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of video decoding MPSoC for wireless video intercom
Wireless video interphone cannot only provide portability, but also connect people through video communication, so it gains more and more interest in consumer electronics. To design such systems, it needs high performance video processing engine. In this paper, a Multi-processor system on a chip (MPSoC) is designed, in which there are one 32-bit RISC CPU and a low power, high performance H.264 codec. The RISC CPU controls the system operation, and the H.264 codec is responsible for video decoding. Due to the large number of data to be processed, an off-chip DDRII SDRAM is used to store source stream and intermediate data. Additionally, the MPSoC can receive real-time wireless video and convert the decoded data into RGB data format that can be displayed on LCD. The MPSoC is implemented on EP3C120F780C8N FPGA, and takes up 71% resource of the total device resource. Experiment results show that it runs 32MHz, and can perform real-time video decoding, with the frame rate up to 30fps.