{"title":"测试电路，用于精确测量存储器的设置/保持和访问时间","authors":"Neha Agarwal","doi":"10.1109/ICMTS.2015.7106153","DOIUrl":null,"url":null,"abstract":"This paper will examine the latest developments in the field of designing the test circuits for accurate measurement of setup/hold and access time of memory IPs. Measurement across all voltage domain and temperature corners, by way of the architecture discussed, has a fine resolution of just two inverter delay and correlates well with silicon within permissible range.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Test circuit for accurate measurement of setup/hold and access time of memories\",\"authors\":\"Neha Agarwal\",\"doi\":\"10.1109/ICMTS.2015.7106153\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper will examine the latest developments in the field of designing the test circuits for accurate measurement of setup/hold and access time of memory IPs. Measurement across all voltage domain and temperature corners, by way of the architecture discussed, has a fine resolution of just two inverter delay and correlates well with silicon within permissible range.\",\"PeriodicalId\":177627,\"journal\":{\"name\":\"Proceedings of the 2015 International Conference on Microelectronic Test Structures\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-03-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2015 International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2015.7106153\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2015.7106153","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Test circuit for accurate measurement of setup/hold and access time of memories
This paper will examine the latest developments in the field of designing the test circuits for accurate measurement of setup/hold and access time of memory IPs. Measurement across all voltage domain and temperature corners, by way of the architecture discussed, has a fine resolution of just two inverter delay and correlates well with silicon within permissible range.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
