有源体偏置SOI-CMOS驱动电路

Wada, Ueda, Hirota, Hirano, Mashiko, Hamano
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We propose in this paper active body-bias SOI-CMOS driver circuits that can operate at high-speed and the supply voltage higher than the built-in voltage. This driver circuit, like the active pull-down scheme in ECL circuits [3], enhances its driving capability during the transition period. The circuit simulations indicated that the proposed circuit operates 55% faster than the bulk driver circuit at 0.8V and 60pF. Circuit Description Fig.2 shows the driver circuits we propose. The output inverter gate, one PMOS and one NMOS, is replaced with six transistors indicated in the broken-line box. The operation of the type-A circuit shown in Fig.2 (a) is as follows. When IN is \"L\", INB is \"H\" and OUT is \"L\". Transistor P1 is on and N1 is off. The feedback signal from OUT turns on P2 and turns off N2. When IN changes from \"L\" to \"H\", P1 turns off and N1 turns on. At this time, P3, P2 and N1 are all on and a DC current flows slightly through P3, P2 and N1, as shown in Fig.3, if we design the transistor P3 to be small. Then the body potential of the transistor P4 falls and the threshold voltage of P4 becomes smaller. Consequently OUT goes to \"H\" quickly. When OUT becomes \"H\", P2 turns off and N2 turns on. The DC current path is cut off and the body potential of P4 becomes the supply voltage level. Thus, the extra power consumptions are minimized in the circuit. In this driver, the body voltages of the output transistors can be adjusted below the built-in voltage if we optimize the transistor sizes of N2, N3, P2 and P3. The body regions of the output transistors are charged or discharged through the transistors, not through diodes. Therefore, the proposed circuit can operate at high-frequency even when the supply voltage exceeds the built-in voltage. In the type-B circuit shown in Fig.2 (b), the feedback signal is replaced by the output signal of the small-size inverter INV to obtain the longer period of the low threshold voltage of P4 or N4. Circuit Simulation Table 1 shows the device parameters of the SO1 and the bulk devices used for the circuit simulations. Fig.4 shows the operating waveforms of the bulk, the conventional SO1 and the type-A SO1 circuit at 1.OV and 60pF. The operating frequency is 100MHz. The body potential of the output transistor, P4 or N4, changes synchronously with the change of INB signal. Therefore, the transistor can drive the load capacitance quickly. As soon as OUT goes to \"H\" or \"L\", the body potential returns to its original state of the gnd or the supply voltage level. Fig.5 shows how the supply voltage affects the delay time and the power dissipation at 60pF. At the supply voltage of l.OV, the type-A SO1 circuit operates 23% faster than the conventional SO1 and 37% faster than the bulk. The extra power loss of the type-A SO1 circuit is 2.4% of the conventional SOI. Compared with the bulk, the type-A SO1 circuit has the 4.0% less power dissipation. As the supply voltage lowers, the advantages of the proposed circuits over the conventional SO1 increase. The type-A SO1 circuit runs 20% faster at 1.2V and 37% faster at 0.8V than the conventional SOI. Fig.6 shows how the load capacitance affects the delay time and the power dissipation at 1.OV. As the load capacitance increases, the advantages of the proposed circuits over the convcntional SO1 increase. The type-A SO1 circuit operates 24% faster at 20pF and 28% faster at lOOpF than the conventional SOI. Compared with the bulk, the type-A SO1 circuit operates 40% faster at 20pF and 36% faster at 100pF. As shown in Fig.5 and Fig.6, the type-B SO1 circuit operates faster than the type-A SO1 circuit. The type-B SO1 circuit operates 12% faster than the type-A SO1 circuit at 0.0' and 60pF. At the same conditions, type-B SO1 circuit operates 55% faster than the bulk circuit. Conclusion This paper describes active body-bias SOI-CMOS driver circuits that operate at high-speed and the supply voltage of over the built-in voltage. The proposed circuits show excellent speed performances over bulk ones even at large load capacitances by replacing the output inverter in driver circuits with the proposed ones. References [ I ] T. Fuse, et al, \"OSV SO1 CMOS Pass-Gate Logic,\" ISSCC Dig. Tech., pp. 88-89, 1996. [2] T. Douseki, et al, \"A 0.5V SIMOX-MTCMOS Circuit with 200ps Logic Gate,\" ISSCC Dig. Tech., pp. 88-89, 1996. [3] K. Ueda, N. Sasaki, H. Sato, and K. Mashiko, \"A Fully Compensated Active Pull-Down ECL Circuit with SelfAdjusting Driving Capability,\" IEEE J. Solid-Sfate Circuits, Vol. 31, NO. 1, pp. 46-53, 1996.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Active Body-bias SOI-CMOS Driver Circuits\",\"authors\":\"Wada, Ueda, Hirota, Hirano, Mashiko, Hamano\",\"doi\":\"10.1109/VLSIC.1997.623786\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Introduction SO1 devices operate faster and consume less power than bulk ones due to their small junction capacitances. However, this advantage decreases as the fan-outs get larger or metalwiring gets longer, because SO1 structures have lesser effects on gate capacitance or wiring capacitance. The body-bias controlled gate [l] shown in Fig.1 (a) can drive large load capacitances. However, this device cannot have the supply voltage of over the junction built-in voltage ( O N ) . The body-bias controlled gate with reverse-biased diodes [2] shown in Fig.1 (b) can operate stably with the supply voltage above the built-in voltage. However, the device operation becomes unstable at high-frequency because the excessive charges in the body cannot be discharged quickly as the diodes are reversely biased. We propose in this paper active body-bias SOI-CMOS driver circuits that can operate at high-speed and the supply voltage higher than the built-in voltage. This driver circuit, like the active pull-down scheme in ECL circuits [3], enhances its driving capability during the transition period. The circuit simulations indicated that the proposed circuit operates 55% faster than the bulk driver circuit at 0.8V and 60pF. Circuit Description Fig.2 shows the driver circuits we propose. The output inverter gate, one PMOS and one NMOS, is replaced with six transistors indicated in the broken-line box. The operation of the type-A circuit shown in Fig.2 (a) is as follows. When IN is \\\"L\\\", INB is \\\"H\\\" and OUT is \\\"L\\\". Transistor P1 is on and N1 is off. The feedback signal from OUT turns on P2 and turns off N2. When IN changes from \\\"L\\\" to \\\"H\\\", P1 turns off and N1 turns on. At this time, P3, P2 and N1 are all on and a DC current flows slightly through P3, P2 and N1, as shown in Fig.3, if we design the transistor P3 to be small. Then the body potential of the transistor P4 falls and the threshold voltage of P4 becomes smaller. Consequently OUT goes to \\\"H\\\" quickly. When OUT becomes \\\"H\\\", P2 turns off and N2 turns on. The DC current path is cut off and the body potential of P4 becomes the supply voltage level. Thus, the extra power consumptions are minimized in the circuit. In this driver, the body voltages of the output transistors can be adjusted below the built-in voltage if we optimize the transistor sizes of N2, N3, P2 and P3. The body regions of the output transistors are charged or discharged through the transistors, not through diodes. Therefore, the proposed circuit can operate at high-frequency even when the supply voltage exceeds the built-in voltage. In the type-B circuit shown in Fig.2 (b), the feedback signal is replaced by the output signal of the small-size inverter INV to obtain the longer period of the low threshold voltage of P4 or N4. Circuit Simulation Table 1 shows the device parameters of the SO1 and the bulk devices used for the circuit simulations. Fig.4 shows the operating waveforms of the bulk, the conventional SO1 and the type-A SO1 circuit at 1.OV and 60pF. The operating frequency is 100MHz. The body potential of the output transistor, P4 or N4, changes synchronously with the change of INB signal. Therefore, the transistor can drive the load capacitance quickly. As soon as OUT goes to \\\"H\\\" or \\\"L\\\", the body potential returns to its original state of the gnd or the supply voltage level. Fig.5 shows how the supply voltage affects the delay time and the power dissipation at 60pF. At the supply voltage of l.OV, the type-A SO1 circuit operates 23% faster than the conventional SO1 and 37% faster than the bulk. The extra power loss of the type-A SO1 circuit is 2.4% of the conventional SOI. Compared with the bulk, the type-A SO1 circuit has the 4.0% less power dissipation. As the supply voltage lowers, the advantages of the proposed circuits over the conventional SO1 increase. The type-A SO1 circuit runs 20% faster at 1.2V and 37% faster at 0.8V than the conventional SOI. Fig.6 shows how the load capacitance affects the delay time and the power dissipation at 1.OV. As the load capacitance increases, the advantages of the proposed circuits over the convcntional SO1 increase. The type-A SO1 circuit operates 24% faster at 20pF and 28% faster at lOOpF than the conventional SOI. Compared with the bulk, the type-A SO1 circuit operates 40% faster at 20pF and 36% faster at 100pF. As shown in Fig.5 and Fig.6, the type-B SO1 circuit operates faster than the type-A SO1 circuit. The type-B SO1 circuit operates 12% faster than the type-A SO1 circuit at 0.0' and 60pF. At the same conditions, type-B SO1 circuit operates 55% faster than the bulk circuit. Conclusion This paper describes active body-bias SOI-CMOS driver circuits that operate at high-speed and the supply voltage of over the built-in voltage. The proposed circuits show excellent speed performances over bulk ones even at large load capacitances by replacing the output inverter in driver circuits with the proposed ones. References [ I ] T. Fuse, et al, \\\"OSV SO1 CMOS Pass-Gate Logic,\\\" ISSCC Dig. Tech., pp. 88-89, 1996. [2] T. Douseki, et al, \\\"A 0.5V SIMOX-MTCMOS Circuit with 200ps Logic Gate,\\\" ISSCC Dig. Tech., pp. 88-89, 1996. [3] K. Ueda, N. Sasaki, H. Sato, and K. Mashiko, \\\"A Fully Compensated Active Pull-Down ECL Circuit with SelfAdjusting Driving Capability,\\\" IEEE J. Solid-Sfate Circuits, Vol. 31, NO. 1, pp. 46-53, 1996.\",\"PeriodicalId\":175678,\"journal\":{\"name\":\"Symposium 1997 on VLSI Circuits\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1997 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1997.623786\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1997 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1997.623786","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

摘要

SO1器件由于其小的结电容而比本体器件运行更快,功耗更低。然而,随着扇出变大或金属布线变长,这种优势会减少,因为SO1结构对栅极电容或布线电容的影响较小。如图1 (a)所示的体偏控制栅极[l]可以驱动较大的负载电容。但是,该器件的供电电压不能超过结内置电压(O N)。如图1 (b)所示,具有反偏二极管的体偏控制栅极[2]可以在电源电压高于内置电压的情况下稳定工作。然而,由于二极管反向偏置,体内的过量电荷不能快速放电,器件在高频下工作变得不稳定。本文提出一种有源体偏置SOI-CMOS驱动电路,可以在高速下工作,且电源电压高于内置电压。该驱动电路与ECL电路中的有源下拉方案[3]一样,在过渡时期增强了驱动能力。电路仿真表明,该电路在0.8V和60pF下的工作速度比本体驱动电路快55%。图2显示了我们提出的驱动电路。输出逆变器门,一个PMOS和一个NMOS,替换为折线框中所示的六个晶体管。图2 (a)所示a型电路的工作原理如下:当IN为“L”时,INB为“H”,OUT为“L”。晶体管P1处于开启状态,N1处于关闭状态。来自OUT的反馈信号打开P2,关闭N2。当IN由“L”变为“H”时,P1关闭,N1打开。此时,P3、P2和N1都处于导通状态,如果我们将晶体管P3设计得较小,则有直流电流轻微流过P3、P2和N1,如图3所示。这时晶体管P4的体电位下降,P4的阈值电压变小。结果OUT很快转到“H”。当OUT变成“H”时,P2关闭,N2打开。直流电流通路被切断,P4的体电位变为电源电压电平。因此,额外的电力消耗是最小的电路。在该驱动器中,通过优化N2, N3, P2和P3的晶体管尺寸,可以将输出晶体管的体电压调整到低于内置电压。输出晶体管的本体区域通过晶体管充电或放电,而不是通过二极管。因此,即使电源电压超过内置电压,所提出的电路也可以在高频下工作。在图2 (b)所示的b型电路中,将反馈信号替换为小尺寸逆变器INV的输出信号,以获得P4或N4较长周期的低阈值电压。表1给出了SO1和用于电路仿真的批量器件的器件参数。图4为本体、常规SO1和a型SO1电路在1时的工作波形。OV和60pF。工作频率为100MHz。输出晶体管P4或N4的体电位随INB信号的变化而同步变化。因此,晶体管可以快速驱动负载电容。一旦OUT转到“H”或“L”,体电位就返回到地或电源电压电平的原始状态。图5显示了60pF时电源电压对延迟时间和功耗的影响。在lv电压下,a型SO1电路的工作速度比传统SO1快23%,比本体快37%。a型SO1电路的额外功率损耗为常规SOI的2.4%。与本体电路相比,a型SO1电路的功耗降低4.0%。随着电源电压的降低,所提出的电路比传统的SO1电路的优点增加。a型SO1电路在1.2V时比传统SOI快20%,在0.8V时比传统SOI快37%。图6显示了负载电容在1 v时对延迟时间和功耗的影响。随着负载电容的增加,所提出的电路比传统的SO1电路的优势增加。a型SO1电路在20pF时比传统SOI快24%,在lOOpF时比传统SOI快28%。与本体相比,a型SO1电路在20pF时工作速度快40%,在100pF时工作速度快36%。如图5和图6所示,b型SO1电路的工作速度比a型SO1电路快。在0.0'和60pF时,b型SO1电路比a型SO1电路工作速度快12%。在相同条件下,b型SO1电路的工作速度比本体电路快55%。本文描述了一种工作在高速、供电电压超过内置电压的有源体偏置SOI-CMOS驱动电路。通过将驱动电路中的输出逆变器替换为所提出的电路,即使在大负载电容下,该电路也比散装电路具有优异的速度性能。参考文献[I] T。
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Active Body-bias SOI-CMOS Driver Circuits
Introduction SO1 devices operate faster and consume less power than bulk ones due to their small junction capacitances. However, this advantage decreases as the fan-outs get larger or metalwiring gets longer, because SO1 structures have lesser effects on gate capacitance or wiring capacitance. The body-bias controlled gate [l] shown in Fig.1 (a) can drive large load capacitances. However, this device cannot have the supply voltage of over the junction built-in voltage ( O N ) . The body-bias controlled gate with reverse-biased diodes [2] shown in Fig.1 (b) can operate stably with the supply voltage above the built-in voltage. However, the device operation becomes unstable at high-frequency because the excessive charges in the body cannot be discharged quickly as the diodes are reversely biased. We propose in this paper active body-bias SOI-CMOS driver circuits that can operate at high-speed and the supply voltage higher than the built-in voltage. This driver circuit, like the active pull-down scheme in ECL circuits [3], enhances its driving capability during the transition period. The circuit simulations indicated that the proposed circuit operates 55% faster than the bulk driver circuit at 0.8V and 60pF. Circuit Description Fig.2 shows the driver circuits we propose. The output inverter gate, one PMOS and one NMOS, is replaced with six transistors indicated in the broken-line box. The operation of the type-A circuit shown in Fig.2 (a) is as follows. When IN is "L", INB is "H" and OUT is "L". Transistor P1 is on and N1 is off. The feedback signal from OUT turns on P2 and turns off N2. When IN changes from "L" to "H", P1 turns off and N1 turns on. At this time, P3, P2 and N1 are all on and a DC current flows slightly through P3, P2 and N1, as shown in Fig.3, if we design the transistor P3 to be small. Then the body potential of the transistor P4 falls and the threshold voltage of P4 becomes smaller. Consequently OUT goes to "H" quickly. When OUT becomes "H", P2 turns off and N2 turns on. The DC current path is cut off and the body potential of P4 becomes the supply voltage level. Thus, the extra power consumptions are minimized in the circuit. In this driver, the body voltages of the output transistors can be adjusted below the built-in voltage if we optimize the transistor sizes of N2, N3, P2 and P3. The body regions of the output transistors are charged or discharged through the transistors, not through diodes. Therefore, the proposed circuit can operate at high-frequency even when the supply voltage exceeds the built-in voltage. In the type-B circuit shown in Fig.2 (b), the feedback signal is replaced by the output signal of the small-size inverter INV to obtain the longer period of the low threshold voltage of P4 or N4. Circuit Simulation Table 1 shows the device parameters of the SO1 and the bulk devices used for the circuit simulations. Fig.4 shows the operating waveforms of the bulk, the conventional SO1 and the type-A SO1 circuit at 1.OV and 60pF. The operating frequency is 100MHz. The body potential of the output transistor, P4 or N4, changes synchronously with the change of INB signal. Therefore, the transistor can drive the load capacitance quickly. As soon as OUT goes to "H" or "L", the body potential returns to its original state of the gnd or the supply voltage level. Fig.5 shows how the supply voltage affects the delay time and the power dissipation at 60pF. At the supply voltage of l.OV, the type-A SO1 circuit operates 23% faster than the conventional SO1 and 37% faster than the bulk. The extra power loss of the type-A SO1 circuit is 2.4% of the conventional SOI. Compared with the bulk, the type-A SO1 circuit has the 4.0% less power dissipation. As the supply voltage lowers, the advantages of the proposed circuits over the conventional SO1 increase. The type-A SO1 circuit runs 20% faster at 1.2V and 37% faster at 0.8V than the conventional SOI. Fig.6 shows how the load capacitance affects the delay time and the power dissipation at 1.OV. As the load capacitance increases, the advantages of the proposed circuits over the convcntional SO1 increase. The type-A SO1 circuit operates 24% faster at 20pF and 28% faster at lOOpF than the conventional SOI. Compared with the bulk, the type-A SO1 circuit operates 40% faster at 20pF and 36% faster at 100pF. As shown in Fig.5 and Fig.6, the type-B SO1 circuit operates faster than the type-A SO1 circuit. The type-B SO1 circuit operates 12% faster than the type-A SO1 circuit at 0.0' and 60pF. At the same conditions, type-B SO1 circuit operates 55% faster than the bulk circuit. Conclusion This paper describes active body-bias SOI-CMOS driver circuits that operate at high-speed and the supply voltage of over the built-in voltage. The proposed circuits show excellent speed performances over bulk ones even at large load capacitances by replacing the output inverter in driver circuits with the proposed ones. References [ I ] T. Fuse, et al, "OSV SO1 CMOS Pass-Gate Logic," ISSCC Dig. Tech., pp. 88-89, 1996. [2] T. Douseki, et al, "A 0.5V SIMOX-MTCMOS Circuit with 200ps Logic Gate," ISSCC Dig. Tech., pp. 88-89, 1996. [3] K. Ueda, N. Sasaki, H. Sato, and K. Mashiko, "A Fully Compensated Active Pull-Down ECL Circuit with SelfAdjusting Driving Capability," IEEE J. Solid-Sfate Circuits, Vol. 31, NO. 1, pp. 46-53, 1996.
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