利用设计中现有的容错电路进行节能扫描测试

Anthi Anastasiou, Y. Tsiatouhas
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引用次数: 1

摘要

时序误差是现代集成电路的主要威胁。存在合适的容错设计技术,比如Razor,旨在应对这种情况。然而,这些解决方案的硅面积成本使它们不适合广泛使用。在本文中,为了扩大时序容错技术的适用性,我们探索了将其扩展到低功耗扫描测试操作的能力。提出了Razor技术的低功耗扫描版本,通过消除扫描操作期间组合逻辑输入端的信号转换,大大降低了扫描功耗。
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Power efficient scan testing by exploiting existing error tolerance circuitry in a design
Timing errors are a major threat in modern integrated circuits. Suitable error tolerance design techniques exist, like Razor, aiming to confront with this situation. However, the silicon area cost of these solutions makes them unattractive for widespread use. In this paper, aiming to broaden the applicability of timing error tolerance techniques, we explore the ability to extend their use for low power scan testing operations. A low power scan version of the Razor technique is presented, which drastically reduces the scan power consumption by eliminating the signal transitions at the input of the combinational logic during the scan operations.
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