Pub Date : 2014-07-08DOI: 10.1109/ETS.2014.6847819
Jia Li, Zhuolei Huang, Weibing Wang
MEMS devices are expected to be used in a growing number of high-volume and low-cost applications. However because they usually require complex test stimuli rather than simple digital electronic signals as common VLSI systems to verify their specifications, testing and calibration costs have actually become a bottleneck to reduce the overall production cost of MEMS sensors. To address this issue, this paper presents an on-chip scheme to calibrate the responsivity of infrared thermopile temperature sensor with digital control signals. With the proposed method, the responsivity related to the ambient temperature can be calibrated before the target temperature being measured thus to achieve accurate temperature measurement. The proposed self-calibrating thermopile sensor design has been realized by CMOS-compatible process to prove the effectiveness of the self-calibration temperature measurement method.
{"title":"Built-in self-calibration of CMOS-compatible thermopile sensor with on-chip electrical stimulus","authors":"Jia Li, Zhuolei Huang, Weibing Wang","doi":"10.1109/ETS.2014.6847819","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847819","url":null,"abstract":"MEMS devices are expected to be used in a growing number of high-volume and low-cost applications. However because they usually require complex test stimuli rather than simple digital electronic signals as common VLSI systems to verify their specifications, testing and calibration costs have actually become a bottleneck to reduce the overall production cost of MEMS sensors. To address this issue, this paper presents an on-chip scheme to calibrate the responsivity of infrared thermopile temperature sensor with digital control signals. With the proposed method, the responsivity related to the ambient temperature can be calibrated before the target temperature being measured thus to achieve accurate temperature measurement. The proposed self-calibrating thermopile sensor design has been realized by CMOS-compatible process to prove the effectiveness of the self-calibration temperature measurement method.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116079405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/ETS.2014.6847846
I. Voyiatzis
In this work, we combine the input vector monitoring concurrent BIST paradigm with input reduction (in order to reduce the Concurrent Test Latency) and Space Compaction of the output responses (in order to reduce the hardware overhead) and examine its implementation on the concurrent testing of sequential modules.
{"title":"Concurrent online BIST for sequential circuits exploiting input reduction and output space compaction","authors":"I. Voyiatzis","doi":"10.1109/ETS.2014.6847846","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847846","url":null,"abstract":"In this work, we combine the input vector monitoring concurrent BIST paradigm with input reduction (in order to reduce the Concurrent Test Latency) and Space Compaction of the output responses (in order to reduce the hardware overhead) and examine its implementation on the concurrent testing of sequential modules.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125897488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/ETS.2014.6847826
A. Prabhu, Vlado Vorisek, H. Lang, Thomas Schumann
With the semiconductor manufacturing development following the trend into very-deep sub-micron technologies and thus making Moore's law a reality, the decrease in node size introduces new defect mechanisms in manufacturing. Still, the strict quality requirements especially related to the automotive industry stay the same. Traditional fault models like stuck-at and transition delay models which have been used for the digital logic of System-on-Chip designs may be successful in detecting most of the manufacturing defects, but not all of them. In this paper, the new Cell Aware fault model, which has been introduced by Mentor Graphics®, is being evaluated for usage in the automotive design process of Freescale™. Using a state-of-the-art microcontroller product manufactured in a CMOS 55nm process technology, the fault model is evaluated for test coverage and test cost (pattern count) and compared against the traditional fault models used by Freescale. The analysis is carried out by performing several experiments, especially focusing on reducing the test pattern count overhead.
{"title":"Analysis of cell-aware test pattern effectiveness — A case study using a 32-bit automotive microcontroller","authors":"A. Prabhu, Vlado Vorisek, H. Lang, Thomas Schumann","doi":"10.1109/ETS.2014.6847826","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847826","url":null,"abstract":"With the semiconductor manufacturing development following the trend into very-deep sub-micron technologies and thus making Moore's law a reality, the decrease in node size introduces new defect mechanisms in manufacturing. Still, the strict quality requirements especially related to the automotive industry stay the same. Traditional fault models like stuck-at and transition delay models which have been used for the digital logic of System-on-Chip designs may be successful in detecting most of the manufacturing defects, but not all of them. In this paper, the new Cell Aware fault model, which has been introduced by Mentor Graphics®, is being evaluated for usage in the automotive design process of Freescale™. Using a state-of-the-art microcontroller product manufactured in a CMOS 55nm process technology, the fault model is evaluated for test coverage and test cost (pattern count) and compared against the traditional fault models used by Freescale. The analysis is carried out by performing several experiments, especially focusing on reducing the test pattern count overhead.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125317483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/ETS.2014.6847829
E. Böhl, Matthew Lewis, Klaus Damm
Deterministic random bit generators can be used for cryptographic operations. An important feature of the DREG is collision resistance in order to avoid the generation of the same output sequence for different seeds. Further features are reverse calculation resistance and fault attack detection, which can in our design be reached by the COSSMA approach (COmplete Set of State MAchines) in combination with the use of one way functions and code checkers respectively. In difference to the usual approaches utilizing hash functions and block ciphers the COSSMA approach grants inherent properties which simplify the detection of fault attacks and provide also protection against side channel attacks with very low overhead.
{"title":"A collision resistant deterministic random bit generator with fault attack detection possibilities","authors":"E. Böhl, Matthew Lewis, Klaus Damm","doi":"10.1109/ETS.2014.6847829","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847829","url":null,"abstract":"Deterministic random bit generators can be used for cryptographic operations. An important feature of the DREG is collision resistance in order to avoid the generation of the same output sequence for different seeds. Further features are reverse calculation resistance and fault attack detection, which can in our design be reached by the COSSMA approach (COmplete Set of State MAchines) in combination with the use of one way functions and code checkers respectively. In difference to the usual approaches utilizing hash functions and block ciphers the COSSMA approach grants inherent properties which simplify the detection of fault attacks and provide also protection against side channel attacks with very low overhead.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125337230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/ETS.2014.6847835
Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, C. Li, M. Hsiao, Laung-Terng Wang
A GPU-based timing-aware ATPG is proposed to generate a compact high-quality test set. The test generation algorithm backtraces and propagates along multiple long paths so that many test patterns are generated at the same time. Generated test patterns are then fault simulated and selected. Compared with an 8-core CPU-based timing-aware commercial ATPG, the proposed GPU-based technique achieved 36% test length reductions on large benchmark circuits while the SDQL quality remains almost the same.
{"title":"GPU-based timing-aware test generation for small delay defects","authors":"Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, C. Li, M. Hsiao, Laung-Terng Wang","doi":"10.1109/ETS.2014.6847835","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847835","url":null,"abstract":"A GPU-based timing-aware ATPG is proposed to generate a compact high-quality test set. The test generation algorithm backtraces and propagates along multiple long paths so that many test patterns are generated at the same time. Generated test patterns are then fault simulated and selected. Compared with an 8-core CPU-based timing-aware commercial ATPG, the proposed GPU-based technique achieved 36% test length reductions on large benchmark circuits while the SDQL quality remains almost the same.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114912551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/ETS.2014.6847839
Arezoo Kamran, Z. Navabi
In response to reliability challenges of new systems being built, we are proposing a scalable Self-Test architecture for many-core processor systems. This BIST architecture periodically distributes test stimuli among identical processing cores in a many-core processor system, suspends normal operation of individual processing cores, applies test, detects faulty cores, and removes them from the system if any are found faulty. Test is continuously performed without any perceptible down-time to the end-user, realizing a many-core processor system with self-healing capability.
{"title":"Homogeneous many-core processor system test distribution and execution mechanism","authors":"Arezoo Kamran, Z. Navabi","doi":"10.1109/ETS.2014.6847839","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847839","url":null,"abstract":"In response to reliability challenges of new systems being built, we are proposing a scalable Self-Test architecture for many-core processor systems. This BIST architecture periodically distributes test stimuli among identical processing cores in a many-core processor system, suspends normal operation of individual processing cores, applies test, detects faulty cores, and removes them from the system if any are found faulty. Test is continuously performed without any perceptible down-time to the end-user, realizing a many-core processor system with self-healing capability.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129621171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/ETS.2014.6847796
A. Cook, H. Wunderlich
Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.
{"title":"Diagnosis of multiple faults with highly compacted test responses","authors":"A. Cook, H. Wunderlich","doi":"10.1109/ETS.2014.6847796","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847796","url":null,"abstract":"Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"792 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114049064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/ETS.2014.6847834
Anthi Anastasiou, Y. Tsiatouhas
Timing errors are a major threat in modern integrated circuits. Suitable error tolerance design techniques exist, like Razor, aiming to confront with this situation. However, the silicon area cost of these solutions makes them unattractive for widespread use. In this paper, aiming to broaden the applicability of timing error tolerance techniques, we explore the ability to extend their use for low power scan testing operations. A low power scan version of the Razor technique is presented, which drastically reduces the scan power consumption by eliminating the signal transitions at the input of the combinational logic during the scan operations.
{"title":"Power efficient scan testing by exploiting existing error tolerance circuitry in a design","authors":"Anthi Anastasiou, Y. Tsiatouhas","doi":"10.1109/ETS.2014.6847834","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847834","url":null,"abstract":"Timing errors are a major threat in modern integrated circuits. Suitable error tolerance design techniques exist, like Razor, aiming to confront with this situation. However, the silicon area cost of these solutions makes them unattractive for widespread use. In this paper, aiming to broaden the applicability of timing error tolerance techniques, we explore the ability to extend their use for low power scan testing operations. A low power scan version of the Razor technique is presented, which drastically reduces the scan power consumption by eliminating the signal transitions at the input of the combinational logic during the scan operations.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124475024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/ETS.2014.6847809
Álvaro Gómez-Pau, L. Balado, J. Figueras
Binning of IC circuits after volume fabrication is widely used to separate tested circuits in different classes depending on different degrees of specifications compliance. When the specifications are directly measured, the boundaries of the classes are usually linear functions in the specification space. For alternate testing strategies the indirect measures generate more complicated regions in the measure space due to the non linear mapping between the specification space and the measure space. The binning strategy proposed in this paper works with the same efficiency regardless of the shape of the boundaries of each binning region. A digital encoding of the measure space using octrees is the key idea of the proposal. The strategy has two phases: (1) The training to generate the digital codes for the binning subsets and (2) the actual production binning of the fabricated ICs. The first phase is performed only once and requires sufficient samples of each binning class to generate the octree under realistic variations. The second phase is fast and requires only to evaluate the octree using the measures of the tested IC. In order to illustrate the proposal, the method has been applied to a Biquad filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages in terms of binning speed. In addition, the method has been compared to a SVM classifier revealing substantial benefits.
{"title":"M-S specification binning based on digitally coded indirect measurements","authors":"Álvaro Gómez-Pau, L. Balado, J. Figueras","doi":"10.1109/ETS.2014.6847809","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847809","url":null,"abstract":"Binning of IC circuits after volume fabrication is widely used to separate tested circuits in different classes depending on different degrees of specifications compliance. When the specifications are directly measured, the boundaries of the classes are usually linear functions in the specification space. For alternate testing strategies the indirect measures generate more complicated regions in the measure space due to the non linear mapping between the specification space and the measure space. The binning strategy proposed in this paper works with the same efficiency regardless of the shape of the boundaries of each binning region. A digital encoding of the measure space using octrees is the key idea of the proposal. The strategy has two phases: (1) The training to generate the digital codes for the binning subsets and (2) the actual production binning of the fabricated ICs. The first phase is performed only once and requires sufficient samples of each binning class to generate the octree under realistic variations. The second phase is fast and requires only to evaluate the octree using the measures of the tested IC. In order to illustrate the proposal, the method has been applied to a Biquad filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages in terms of binning speed. In addition, the method has been compared to a SVM classifier revealing substantial benefits.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124784334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-26DOI: 10.1109/ETS.2014.6847836
I. Voyiatzis
In this work we present a new scheme for the on-chip application of test patterns utilizing an accumulator structure whose inputs are driven by a barrel shifter. The consecutive patterns applied to the inputs of the Circuit Under Test differ in one bit, therefore the power consumed is lower compared to previously proposed accumulator-based pattern application schemes.
{"title":"Accumulator-based test-per-clock scheme for low-power on-chip application of test patterns","authors":"I. Voyiatzis","doi":"10.1109/ETS.2014.6847836","DOIUrl":"https://doi.org/10.1109/ETS.2014.6847836","url":null,"abstract":"In this work we present a new scheme for the on-chip application of test patterns utilizing an accumulator structure whose inputs are driven by a barrel shifter. The consecutive patterns applied to the inputs of the Circuit Under Test differ in one bit, therefore the power consumed is lower compared to previously proposed accumulator-based pattern application schemes.","PeriodicalId":145416,"journal":{"name":"2014 19th IEEE European Test Symposium (ETS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131352399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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