通过CAD功能启用DIR(可靠性设计)

W. Kang, B. Potts, R. Hokinson, J. Riley, D. Doman, F. Cano, N. Nagaraj, Noel Durrant
{"title":"通过CAD功能启用DIR(可靠性设计)","authors":"W. Kang, B. Potts, R. Hokinson, J. Riley, D. Doman, F. Cano, N. Nagaraj, Noel Durrant","doi":"10.1109/ISQED.2000.838868","DOIUrl":null,"url":null,"abstract":"Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Enabling DIR (Designing-In-Reliability) through CAD capabilities\",\"authors\":\"W. Kang, B. Potts, R. Hokinson, J. Riley, D. Doman, F. Cano, N. Nagaraj, Noel Durrant\",\"doi\":\"10.1109/ISQED.2000.838868\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.\",\"PeriodicalId\":113766,\"journal\":{\"name\":\"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-03-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2000.838868\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2000.838868","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

芯片设计越来越大,越来越复杂。为了应对这些趋势,最近高性能设计中使用的设计方法和工具要求也在迅速变化。SEMATECH成立了一个设计可靠性(DIR)团队,由成员公司的DIR和CAD工具专家组成。该团队的主要目标是定义和开发成员的工具需求,并将这些需求传达给EDA行业,从而促进新的和改进的工具的开发。在本文中,DIR项目目标和建议与优先化的工具需求或差距一起呈现。工具差距分为两类:CAD工具/数据接口和DIR点解决方案。CAD工具/数据接口处理核心设计工具,这些工具可以实现按结构进行更正,例如可靠性约束放置和路由工具。DIR点解决方案是指可靠性仿真或验证工具。此外,提出了前5个优先级刀具需求的高级刀具需求。此外,为了显示当前和未来的DIR工具差距,提出了DIR工具能力的成熟度矩阵。此外,还提供了团队和未来项目的高级路线图。
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Enabling DIR (Designing-In-Reliability) through CAD capabilities
Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.
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