W. Kang, B. Potts, R. Hokinson, J. Riley, D. Doman, F. Cano, N. Nagaraj, Noel Durrant
{"title":"通过CAD功能启用DIR(可靠性设计)","authors":"W. Kang, B. Potts, R. Hokinson, J. Riley, D. Doman, F. Cano, N. Nagaraj, Noel Durrant","doi":"10.1109/ISQED.2000.838868","DOIUrl":null,"url":null,"abstract":"Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Enabling DIR (Designing-In-Reliability) through CAD capabilities\",\"authors\":\"W. Kang, B. Potts, R. Hokinson, J. Riley, D. Doman, F. Cano, N. Nagaraj, Noel Durrant\",\"doi\":\"10.1109/ISQED.2000.838868\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.\",\"PeriodicalId\":113766,\"journal\":{\"name\":\"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-03-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2000.838868\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2000.838868","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Enabling DIR (Designing-In-Reliability) through CAD capabilities
Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.