Jing Cao, Haiqing Lin, Y. Xiang, Chun-Fu Kao, K. Dyer
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引用次数: 17
摘要
提出了一种90 nm CMOS 10位1gs /s电流转向数模转换器。它是为下一代高速数字通信soc而设计和优化的。仅使用5个电源/接地引脚和10位架构，在800 MS/s的41.3 MHz全尺寸输入下测量72 dB SFDR和9.2 ENOB。在1.05 GS/s下，满量程54.3 MHz输入可实现68 dB SFDR。它的核心功耗为49兆瓦，是该性能水平下报告的最低功耗，并且占据的芯片面积仅为0.36 mm2。单片DAC采用台积电1P9M 90nm CMOS工艺制造
A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Applications
A 90 nm CMOS 10-bit 1 GS/s current-steering D/A converter is presented. It is designed and optimized for next generation high-speed digital communication SoCs. With only five power/ground pins and a 10-bit architecture, 72 dB SFDR and 9.2 ENOB are measured with a full-scale 41.3 MHz input at 800 MS/s. At 1.05 GS/s, 68 dB SFDR is achieved for a full-scale 54.3 MHz input. It dissipates a core power of 49 mW, the lowest power consumption reported at this performance level, and occupies a die area of merely 0.36 mm2. The monolithic DAC is fabricated in TSMC 1P9M 90nm CMOS process
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