CMOS组合电路中的栅极泄漏估计与最小化

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI:10.1109/ICM.2003.238361

R.S. Guindi

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引用次数: 4

摘要

本文提出了一种估算和最小化CMOS组合电路中栅极隧道电流总量的方法。我们利用栅极泄漏所表现出的状态依赖性，并利用信号概率来优化内部电路互连。给出了一些ISCAS-85基准电路的测试结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Gate-leakage estimation and minimization in CMOS combinatorial circuits

This work presents a methodology for estimating and minimizing the total amount of gate-tunneling current in CMOS combinatorial circuits. We take advantage of the state-dependency exhibited by the gate-leakage and use signal probabilities to optimize internal circuit interconnections. Results are given for a number of ISCAS-85 benchmark circuits.

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Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)

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