Modeling and simulation of an open-loop architecture ADC

This paper introduces a behavioral simulation of an open loop architecture pipeline ADC. A behavioral model is developed in MATLAB/SIMULINK. The main error sources that affect the ADC are investigated and various non-idealities in an open loop architecture ADC, such as S/H bandwidth limitation, clock jitter, and interpolator gain mismatch, are analyzed. It also shows the impact of nonlinearities on the performance of the ADC. The results aid the design of open loop pipeline ADCs by providing a comprehensive set of design specifications that must be satisfied by each building block.