{"title":"基于校验和在线测试的记忆电阻神经网络鲁棒容错设计","authors":"Michihiro Shintani, Mamoru Ishizaka, M. Inoue","doi":"10.1109/ATS52891.2021.00017","DOIUrl":null,"url":null,"abstract":"The matrix-vector product is the most essential operation in the weight calculation of deep learning, and greatly impacts the calculation speed and power consumption of neural network circuits. A memristor is one of the most promising components used to efficiently develop matrix-vector products. However, it has been pointed out that memristors have a severely low write endurance limitation and large variation during operation owing to their manufacturing immaturity. While an algorithm-based fault tolerance method has thus far been proposed to enhance the reliability by applying checksum function and online testing, the effectiveness of such the function remains limited because it can apply only the forward propagation and multiple hard faults cannot be repaired. This paper proposes an extension of the conventional method to achieve a more robust fault-tolerant method for memristor-based neural network circuits. Numerical experiments using the Hopfield network and three-layered neural network demonstrate that the proposed method achieves 5.25% and 1.88% higher classification accuracies compared with a conventional fault-tolerant method, respectively.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"203 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network\",\"authors\":\"Michihiro Shintani, Mamoru Ishizaka, M. Inoue\",\"doi\":\"10.1109/ATS52891.2021.00017\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The matrix-vector product is the most essential operation in the weight calculation of deep learning, and greatly impacts the calculation speed and power consumption of neural network circuits. A memristor is one of the most promising components used to efficiently develop matrix-vector products. However, it has been pointed out that memristors have a severely low write endurance limitation and large variation during operation owing to their manufacturing immaturity. While an algorithm-based fault tolerance method has thus far been proposed to enhance the reliability by applying checksum function and online testing, the effectiveness of such the function remains limited because it can apply only the forward propagation and multiple hard faults cannot be repaired. This paper proposes an extension of the conventional method to achieve a more robust fault-tolerant method for memristor-based neural network circuits. Numerical experiments using the Hopfield network and three-layered neural network demonstrate that the proposed method achieves 5.25% and 1.88% higher classification accuracies compared with a conventional fault-tolerant method, respectively.\",\"PeriodicalId\":432330,\"journal\":{\"name\":\"2021 IEEE 30th Asian Test Symposium (ATS)\",\"volume\":\"203 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 30th Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS52891.2021.00017\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 30th Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS52891.2021.00017","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network
The matrix-vector product is the most essential operation in the weight calculation of deep learning, and greatly impacts the calculation speed and power consumption of neural network circuits. A memristor is one of the most promising components used to efficiently develop matrix-vector products. However, it has been pointed out that memristors have a severely low write endurance limitation and large variation during operation owing to their manufacturing immaturity. While an algorithm-based fault tolerance method has thus far been proposed to enhance the reliability by applying checksum function and online testing, the effectiveness of such the function remains limited because it can apply only the forward propagation and multiple hard faults cannot be repaired. This paper proposes an extension of the conventional method to achieve a more robust fault-tolerant method for memristor-based neural network circuits. Numerical experiments using the Hopfield network and three-layered neural network demonstrate that the proposed method achieves 5.25% and 1.88% higher classification accuracies compared with a conventional fault-tolerant method, respectively.