Design Methodology of the Output Power Stage of a Step-Down DC-DC Converter

In this work, a design methodology of a step-down (buck) DC-DC converter is presented focusing on the output power stage. The target system is a synchronous buck converter for general purpose applications, which works in a wide range of input and output voltages. The analysis has been focused on the power conversion efficiency that represents one of the major features of this device. Its efficiency is strictly related to the power MOS losses, both conduction and switching ones. The design methodology has been organized into three steps: the first one is the characterization of the power MOS parasites (both resistive and capacitive) with particular attention to temperature and gate driving voltage; in the second step, the power losses are evaluated according to parasitic at different temperature and driving condition of the power MOS; in the last step, the theoretical calculation is verified with the simulation. In particular, the technology used in this work is a 0.16 $\mu \mathrm{m}$ Advanced BCD Technology and the simulation environment used is the Cadence Virtuoso suite.