{"title":"全差分12位100MS/s采样保持模块的优化设计，SFDR超过77dB","authors":"Ke Liu, Hai-gang Yang","doi":"10.1109/ICASIC.2007.4415662","DOIUrl":null,"url":null,"abstract":"A fully differential sample and hold module has been designed for the front-end of a pipeline ADC using 0.35 mum 2P4M CMOS technology with a power supply of 3.3 V. The key design issues include optimization of speed and accuracy. To meet the requirements, a differential flip-around capacitor topology has been used with special care taken in linearization of switches. Gain-boosted OTA with high DC gain and larger bandwidth is designed and optimized. The output of the module can attain over 77dB SFDR, which is suitable for serving as a front-end in a 12bit 100MS/s pipeline ADC.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Optimum design of a fully differential 12bit 100MS/s sample and hold module with over 77dB SFDR\",\"authors\":\"Ke Liu, Hai-gang Yang\",\"doi\":\"10.1109/ICASIC.2007.4415662\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully differential sample and hold module has been designed for the front-end of a pipeline ADC using 0.35 mum 2P4M CMOS technology with a power supply of 3.3 V. The key design issues include optimization of speed and accuracy. To meet the requirements, a differential flip-around capacitor topology has been used with special care taken in linearization of switches. Gain-boosted OTA with high DC gain and larger bandwidth is designed and optimized. The output of the module can attain over 77dB SFDR, which is suitable for serving as a front-end in a 12bit 100MS/s pipeline ADC.\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415662\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415662","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
采用0.35 μ m 2P4M CMOS技术，采用3.3 V电源，为流水线ADC前端设计了一个全差分采样保持模块。关键的设计问题包括速度和精度的优化。为了满足要求，在开关的线性化中特别注意使用了差分翻转电容器拓扑。设计并优化了具有高直流增益和更大带宽的增益增强OTA。该模块的输出可达到77dB以上的SFDR，适合作为12位100MS/s流水线ADC的前端。
Optimum design of a fully differential 12bit 100MS/s sample and hold module with over 77dB SFDR
A fully differential sample and hold module has been designed for the front-end of a pipeline ADC using 0.35 mum 2P4M CMOS technology with a power supply of 3.3 V. The key design issues include optimization of speed and accuracy. To meet the requirements, a differential flip-around capacitor topology has been used with special care taken in linearization of switches. Gain-boosted OTA with high DC gain and larger bandwidth is designed and optimized. The output of the module can attain over 77dB SFDR, which is suitable for serving as a front-end in a 12bit 100MS/s pipeline ADC.
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