{"title":"面向大规模并行计算系统的多路互连网络设计","authors":"T. Takimoto, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.1994.302196","DOIUrl":null,"url":null,"abstract":"The concept of multiplex interconnection networks is proposed to attack the communication crisis in massively parallel computing in the next generation. In the multiplex interconnection network, multiplexable information carriers, such as optical wavelengths, are employed so that large-scale communication topologies can be embedded in the virtual space of multiplexable carriers with reduced interconnections. This paper discusses a systematic multiplexing scheme for the class of interconnection networks defined by bit-permute-complement (BPC) permutations. It is shown that by using the proposed technique, the wiring area can be reduced by less than the factor of 1/r using r kinds of multiplexable components.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of multiplex interconnection networks for massively parallel computing systems\",\"authors\":\"T. Takimoto, T. Aoki, T. Higuchi\",\"doi\":\"10.1109/ISMVL.1994.302196\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The concept of multiplex interconnection networks is proposed to attack the communication crisis in massively parallel computing in the next generation. In the multiplex interconnection network, multiplexable information carriers, such as optical wavelengths, are employed so that large-scale communication topologies can be embedded in the virtual space of multiplexable carriers with reduced interconnections. This paper discusses a systematic multiplexing scheme for the class of interconnection networks defined by bit-permute-complement (BPC) permutations. It is shown that by using the proposed technique, the wiring area can be reduced by less than the factor of 1/r using r kinds of multiplexable components.<<ETX>>\",\"PeriodicalId\":137138,\"journal\":{\"name\":\"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)\",\"volume\":\"90 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1994.302196\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1994.302196","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of multiplex interconnection networks for massively parallel computing systems
The concept of multiplex interconnection networks is proposed to attack the communication crisis in massively parallel computing in the next generation. In the multiplex interconnection network, multiplexable information carriers, such as optical wavelengths, are employed so that large-scale communication topologies can be embedded in the virtual space of multiplexable carriers with reduced interconnections. This paper discusses a systematic multiplexing scheme for the class of interconnection networks defined by bit-permute-complement (BPC) permutations. It is shown that by using the proposed technique, the wiring area can be reduced by less than the factor of 1/r using r kinds of multiplexable components.<>