{"title":"用于高速微处理器的1.2GHz延迟时钟发生器","authors":"I. Jung, Moo-young Kim, Chulwoo Kim","doi":"10.1109/ASPDAC.2008.4484068","DOIUrl":null,"url":null,"abstract":"A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13 um CMOS technology occupies only 0.004 mm and operates at variable input frequencies ranging from 625 MHz to 1.2GHz.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 1.2GHz delayed clock generator for high-speed microprocessors\",\"authors\":\"I. Jung, Moo-young Kim, Chulwoo Kim\",\"doi\":\"10.1109/ASPDAC.2008.4484068\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13 um CMOS technology occupies only 0.004 mm and operates at variable input frequencies ranging from 625 MHz to 1.2GHz.\",\"PeriodicalId\":277556,\"journal\":{\"name\":\"2008 Asia and South Pacific Design Automation Conference\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-01-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 Asia and South Pacific Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.2008.4484068\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Asia and South Pacific Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2008.4484068","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
研制了一种能够根据输入时钟频率调整时钟相位的1.2GHz延时时钟发生器。它由一个全数字CMOS电路组成，导致一个简单，强大和便携的IP。一个周期的锁定时间使时钟按需电路结构。所实现的延迟时钟发生器采用0.13 um CMOS技术，占地仅为0.004 mm，可在625 MHz至1.2GHz的可变输入频率下工作。
A 1.2GHz delayed clock generator for high-speed microprocessors
A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13 um CMOS technology occupies only 0.004 mm and operates at variable input frequencies ranging from 625 MHz to 1.2GHz.
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