采用改进控制逻辑电路的低功耗连续逼近ADC

S. Masoodian, M. A. Khalatbari
{"title":"采用改进控制逻辑电路的低功耗连续逼近ADC","authors":"S. Masoodian, M. A. Khalatbari","doi":"10.1109/IRANIANCEE.2012.6292332","DOIUrl":null,"url":null,"abstract":"In this paper a new control logic circuit for successive approximation register analog-to-digital converter (SA-ADC) is proposed. In the proposed digital circuit architecture, the number of flip-flops is reduced and the flip-flops do not need set and reset nodes. The simulation results of a 5-bit, 100 MS/s ADC in a 0.18-μm technology show that the digital power consumption of the proposed structure is reduced by a factor of 17% and the overall power consumption is reduced around 10% in comparison with the conventional counterpart.","PeriodicalId":308726,"journal":{"name":"20th Iranian Conference on Electrical Engineering (ICEE2012)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A power-efficient successive approximation ADC using an improved control logic circuit\",\"authors\":\"S. Masoodian, M. A. Khalatbari\",\"doi\":\"10.1109/IRANIANCEE.2012.6292332\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a new control logic circuit for successive approximation register analog-to-digital converter (SA-ADC) is proposed. In the proposed digital circuit architecture, the number of flip-flops is reduced and the flip-flops do not need set and reset nodes. The simulation results of a 5-bit, 100 MS/s ADC in a 0.18-μm technology show that the digital power consumption of the proposed structure is reduced by a factor of 17% and the overall power consumption is reduced around 10% in comparison with the conventional counterpart.\",\"PeriodicalId\":308726,\"journal\":{\"name\":\"20th Iranian Conference on Electrical Engineering (ICEE2012)\",\"volume\":\"89 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"20th Iranian Conference on Electrical Engineering (ICEE2012)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRANIANCEE.2012.6292332\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"20th Iranian Conference on Electrical Engineering (ICEE2012)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRANIANCEE.2012.6292332","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

提出了一种用于逐次逼近寄存器模数转换器(SA-ADC)的新型控制逻辑电路。在所提出的数字电路架构中,减少了触发器的数量,并且触发器不需要设置和复位节点。对0.18 μm工艺的5位、100 MS/s ADC的仿真结果表明,与传统结构相比,该结构的数字功耗降低了17%,总功耗降低了10%左右。
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A power-efficient successive approximation ADC using an improved control logic circuit
In this paper a new control logic circuit for successive approximation register analog-to-digital converter (SA-ADC) is proposed. In the proposed digital circuit architecture, the number of flip-flops is reduced and the flip-flops do not need set and reset nodes. The simulation results of a 5-bit, 100 MS/s ADC in a 0.18-μm technology show that the digital power consumption of the proposed structure is reduced by a factor of 17% and the overall power consumption is reduced around 10% in comparison with the conventional counterpart.
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