Integrated CMOS imager for pattern recognition

This paper presents an analog CMOS architecture for on-chip pattern recognition. The system comprises a CMOS imager in the front end followed by low power computation circuitry for determining a match between the captured image and image patterns stored in on-chip memory. The imager has a programmable kernel selector and correlated double sampling circuit for suppression of fixed pattern noise. The closeness of a successful match can be controlled by an input bias current. The prototype with a 6 times 6 pixel array in a 0.5 mum CMOS process is being implemented. This chip can be used for applications requiring dedicated pattern recognition.