K. Biery, K. Ragan, R. Grindley, A. Holscher, P. Sinervo, R. Harris, K. Schurecht, T. Shaw
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The CDF data acquisition system was upgraded for the 1992 run, with modifications to the front-end electronics and the addition of a second FASTBUS-based event builder. The goal is a 35-Hz output rate to the Level 3 trigger processor farm. The initial performance of the system up to the Level 3 input is reviewed and compared to that of a Verilog simulation. The system runs reliably and its performance is in good agreement with the predictions of the behavioral simulation.<>
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