{"title":"9.5mW 4GHz WCDMA频率合成器，0.13/spl mu/m CMOS","authors":"Xinhua Chen, Qiuting Huang","doi":"10.1109/LPE.2005.195487","DOIUrl":null,"url":null,"abstract":"A 4GHz integer-N frequency synthesizer is realized in a 0.13/spl mu/m CMOS technology. It has a 400kHz reference frequency and 40kHz loop bandwidth such that 2GHz quadrature LO signals can be generated after a divide-by-two, with channel raster of 200kHz. The measured in-band phase noise is -74dBc/Hz @4kHz offset. A self-regulated charge pump is proposed to improve matching as well as charge sharing. Reference spurs are thereby kept below -55dBc over the VCO tuning voltage from rail to rail. The requirements for UMTS transceiver have been fulfilled with an overall power consumption of 9.5mW, which is the lowest reported to date. Core area of the chip is as small as 0.2mm/sup 2/.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13/spl mu/m CMOS\",\"authors\":\"Xinhua Chen, Qiuting Huang\",\"doi\":\"10.1109/LPE.2005.195487\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 4GHz integer-N frequency synthesizer is realized in a 0.13/spl mu/m CMOS technology. It has a 400kHz reference frequency and 40kHz loop bandwidth such that 2GHz quadrature LO signals can be generated after a divide-by-two, with channel raster of 200kHz. The measured in-band phase noise is -74dBc/Hz @4kHz offset. A self-regulated charge pump is proposed to improve matching as well as charge sharing. Reference spurs are thereby kept below -55dBc over the VCO tuning voltage from rail to rail. The requirements for UMTS transceiver have been fulfilled with an overall power consumption of 9.5mW, which is the lowest reported to date. Core area of the chip is as small as 0.2mm/sup 2/.\",\"PeriodicalId\":256018,\"journal\":{\"name\":\"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LPE.2005.195487\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LPE.2005.195487","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13/spl mu/m CMOS
A 4GHz integer-N frequency synthesizer is realized in a 0.13/spl mu/m CMOS technology. It has a 400kHz reference frequency and 40kHz loop bandwidth such that 2GHz quadrature LO signals can be generated after a divide-by-two, with channel raster of 200kHz. The measured in-band phase noise is -74dBc/Hz @4kHz offset. A self-regulated charge pump is proposed to improve matching as well as charge sharing. Reference spurs are thereby kept below -55dBc over the VCO tuning voltage from rail to rail. The requirements for UMTS transceiver have been fulfilled with an overall power consumption of 9.5mW, which is the lowest reported to date. Core area of the chip is as small as 0.2mm/sup 2/.
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