1.6 kbps语音合成的低成本VLSI架构设计

2003 IEEE International Conference on Consumer Electronics, 2003. ICCE. Pub Date : 2003-06-17 DOI:10.1109/ICCE.2003.1218910

Chu Yu, Hwai-Tsu Hu

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摘要

我们提出了一种低成本的1.6 kbps语音合成架构。语音合成算法是根据面向硬件的设计来制定的。基于我们提出的语音码器，新架构消耗较少的硬件资源，因此适合硬件实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of a low-cost VLSI architecture for 1.6 kbps speech synthesis

We present a low-cost architecture for speech synthesis at 1.6 kbps. The speech synthesis algorithm is formulated in terms of a hardware-oriented design. Based on our proposed speech vocoder, the novel architecture consumes lower hardware resources and is therefore suited for hardware implementation.

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2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.

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