{"title":"DSP应用中的缓冲存储器要求","authors":"M. Adé, R. Lauwereins, J. Peperstraete","doi":"10.1109/IWRSP.1994.315904","DOIUrl":null,"url":null,"abstract":"Studies synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the construction of a deadlock-free static schedule. We develop a rule to quickly analyze a graph's consistency. A graph is split up into single and parallel paths. Single paths are analysed, as well as the most frequent parallel paths. The results are used in the rapid prototyping environment GRAPE-II in the case where the emulation hardware contains FPGAs, or when memory is critical.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"37","resultStr":"{\"title\":\"Buffer memory requirements in DSP applications\",\"authors\":\"M. Adé, R. Lauwereins, J. Peperstraete\",\"doi\":\"10.1109/IWRSP.1994.315904\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Studies synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the construction of a deadlock-free static schedule. We develop a rule to quickly analyze a graph's consistency. A graph is split up into single and parallel paths. Single paths are analysed, as well as the most frequent parallel paths. The results are used in the rapid prototyping environment GRAPE-II in the case where the emulation hardware contains FPGAs, or when memory is critical.<<ETX>>\",\"PeriodicalId\":261113,\"journal\":{\"name\":\"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"37\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWRSP.1994.315904\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWRSP.1994.315904","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Studies synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the construction of a deadlock-free static schedule. We develop a rule to quickly analyze a graph's consistency. A graph is split up into single and parallel paths. Single paths are analysed, as well as the most frequent parallel paths. The results are used in the rapid prototyping environment GRAPE-II in the case where the emulation hardware contains FPGAs, or when memory is critical.<>
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