Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315896
M. Missikoff, M. Toiati
Presents Mosaico, an integrated environment conceived to support the design and specification of object-oriented database applications. Mosaico assists the designer in producing a formal and correct specification of the application domain in the form of a conceptual schema, a conceptual model of the application functions, and, finally, an executable prototype of the database application. The conceptual model of the database application is constructed by using the design language TQL++ (Type and Query Language++). The resultant TQL++ specification is semantically verified based on the theory underlying TQL++. Furthermore, through rapid prototyping, the TQL++ specification can be functionally verified. Semantic verification guarantees the correctness of the specification within the realm of the formal theory of the language. However, it does not guarantee the "fidelity" of the specification to the real world requirements (i.e. what the users really want). Rapid prototyping and functional verification are a means to bridge that gap.<>
{"title":"Safe rapid prototyping of object-oriented database applications","authors":"M. Missikoff, M. Toiati","doi":"10.1109/IWRSP.1994.315896","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315896","url":null,"abstract":"Presents Mosaico, an integrated environment conceived to support the design and specification of object-oriented database applications. Mosaico assists the designer in producing a formal and correct specification of the application domain in the form of a conceptual schema, a conceptual model of the application functions, and, finally, an executable prototype of the database application. The conceptual model of the database application is constructed by using the design language TQL++ (Type and Query Language++). The resultant TQL++ specification is semantically verified based on the theory underlying TQL++. Furthermore, through rapid prototyping, the TQL++ specification can be functionally verified. Semantic verification guarantees the correctness of the specification within the realm of the formal theory of the language. However, it does not guarantee the \"fidelity\" of the specification to the real world requirements (i.e. what the users really want). Rapid prototyping and functional verification are a means to bridge that gap.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117002316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315902
A. Saha, R. Krishnamurthy
Field programmable gate arrays (FPGAs) provide an innovative and flexible platform to implement and evaluate digital signal processing (DSP) applications. A CAD design methodology which is used to implement DSP algorithms is presented. An introduction is given to the various issues involved in the multi-chip partitioning of large DSP implementations, and approaches towards efficient auto-partitioners are also discussed in detail. The design and implementation of an 8-point 1D discrete cosine transform (DCT) and its inverse (IDCT) on a processor with FPGAs is presented in this paper, as an illustrative example of a typical DSP algorithm. The processor uses 16-bit precision, is implemented on six Xilinx 4000 type FPGAs and operates at 40 MHz.<>
{"title":"Some design issues in multi-chip FPGA implementation of DSP algorithms","authors":"A. Saha, R. Krishnamurthy","doi":"10.1109/IWRSP.1994.315902","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315902","url":null,"abstract":"Field programmable gate arrays (FPGAs) provide an innovative and flexible platform to implement and evaluate digital signal processing (DSP) applications. A CAD design methodology which is used to implement DSP algorithms is presented. An introduction is given to the various issues involved in the multi-chip partitioning of large DSP implementations, and approaches towards efficient auto-partitioners are also discussed in detail. The design and implementation of an 8-point 1D discrete cosine transform (DCT) and its inverse (IDCT) on a processor with FPGAs is presented in this paper, as an illustrative example of a typical DSP algorithm. The processor uses 16-bit precision, is implemented on six Xilinx 4000 type FPGAs and operates at 40 MHz.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121218240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315897
J. Brunel, I. Augé, M. Hervieu, P. Bourquin, Philippe Renaud
A quantitative method for designing application specific integrated (sub)systems is presented. The method uses a general-purpose silicon assembler-ALMA (Approche d'un Langage de Micro-Architecture). We illustrate this approach by the example of a dictionary machine that consists of n processing elements working in parallel. An analysis of the effect of several generic parameters on the performance and the size of the silicon parts exemplifies the quantitative approach to cost/performance tradeoffs that is offered by ALMA.<>
提出了一种定量设计特定应用集成(子系统)系统的方法。该方法使用通用硅汇编器alma (approach d’un language de microarchitecture)。我们通过一个字典机的例子来说明这种方法，这个字典机由n个并行工作的处理元素组成。对几个通用参数对性能和硅部件尺寸的影响的分析举例说明了ALMA提供的成本/性能权衡的定量方法。
{"title":"Quantitative design of a scalable microsystem using ALMA: the example of the dictionary machine","authors":"J. Brunel, I. Augé, M. Hervieu, P. Bourquin, Philippe Renaud","doi":"10.1109/IWRSP.1994.315897","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315897","url":null,"abstract":"A quantitative method for designing application specific integrated (sub)systems is presented. The method uses a general-purpose silicon assembler-ALMA (Approche d'un Langage de Micro-Architecture). We illustrate this approach by the example of a dictionary machine that consists of n processing elements working in parallel. An analysis of the effect of several generic parameters on the performance and the size of the silicon parts exemplifies the quantitative approach to cost/performance tradeoffs that is offered by ALMA.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121710770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315904
M. Adé, R. Lauwereins, J. Peperstraete
Studies synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the construction of a deadlock-free static schedule. We develop a rule to quickly analyze a graph's consistency. A graph is split up into single and parallel paths. Single paths are analysed, as well as the most frequent parallel paths. The results are used in the rapid prototyping environment GRAPE-II in the case where the emulation hardware contains FPGAs, or when memory is critical.<>
{"title":"Buffer memory requirements in DSP applications","authors":"M. Adé, R. Lauwereins, J. Peperstraete","doi":"10.1109/IWRSP.1994.315904","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315904","url":null,"abstract":"Studies synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the construction of a deadlock-free static schedule. We develop a rule to quickly analyze a graph's consistency. A graph is split up into single and parallel paths. Single paths are analysed, as well as the most frequent parallel paths. The results are used in the rapid prototyping environment GRAPE-II in the case where the emulation hardware contains FPGAs, or when memory is critical.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124749547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315891
G. Fisher
Why build application prototypes that cannot be used in the production environments for which they were designed? Prototypes, even if they are to be scrapped, should be built in standardized environments to reduce the cost of reengineering for different environments and to provide better, simpler support. Rapid System Prototyping (RSP) places the emphasis of requirements definition and analysis on uncovering and defining engineering and software requirements in an effort to reduce the risk of system development. This report describes a standards-based framework for supporting RSP. It illustrates the pros and cons of proprietary and nonproprietary solutions to the problems associated with prototyping environments, and introduces a reference model for establishing the framework. This framework is called the Open System Environment (OSE). The specifications and standards recommended in the RSP Open System Environment (RSP/OSE) support RSP by defining a standardized environment and framework in which rapid system prototypes can be used to concentrate the focus on uncovering and defining application requirements, and to provide for the evolution of products in broad-based markets.<>
{"title":"Rapid system prototyping in an open system environment","authors":"G. Fisher","doi":"10.1109/IWRSP.1994.315891","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315891","url":null,"abstract":"Why build application prototypes that cannot be used in the production environments for which they were designed? Prototypes, even if they are to be scrapped, should be built in standardized environments to reduce the cost of reengineering for different environments and to provide better, simpler support. Rapid System Prototyping (RSP) places the emphasis of requirements definition and analysis on uncovering and defining engineering and software requirements in an effort to reduce the risk of system development. This report describes a standards-based framework for supporting RSP. It illustrates the pros and cons of proprietary and nonproprietary solutions to the problems associated with prototyping environments, and introduces a reference model for establishing the framework. This framework is called the Open System Environment (OSE). The specifications and standards recommended in the RSP Open System Environment (RSP/OSE) support RSP by defining a standardized environment and framework in which rapid system prototypes can be used to concentrate the focus on uncovering and defining application requirements, and to provide for the evolution of products in broad-based markets.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129577330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315912
D. Andrews, Andrew Wheeler, B. Wealand, C. Kancler
A custom chip set implementing a single instruction multiple data (SIMD) architecture has been designed bringing the benefits of massively parallel processing to the embedded systems domain. A scaled, rapid prototype was first implemented providing an exact duplicate of the functionality and interfaces of the custom chips, but using off the shelf technology. This scaled version was specified to allow development and debugging of software, and provide early feedback for verification of the interfaces and instruction operations. The rapid prototype provides full functionality, allowing any design errors or beneficial modifications to the design to be identified.<>
{"title":"Rapid prototype of an SIMD processor array (using FPGA's)","authors":"D. Andrews, Andrew Wheeler, B. Wealand, C. Kancler","doi":"10.1109/IWRSP.1994.315912","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315912","url":null,"abstract":"A custom chip set implementing a single instruction multiple data (SIMD) architecture has been designed bringing the benefits of massively parallel processing to the embedded systems domain. A scaled, rapid prototype was first implemented providing an exact duplicate of the functionality and interfaces of the custom chips, but using off the shelf technology. This scaled version was specified to allow development and debugging of software, and provide early feedback for verification of the interfaces and instruction operations. The rapid prototype provides full functionality, allowing any design errors or beneficial modifications to the design to be identified.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129912397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315915
M. Richards
The Rapid Prototyping of Application Specific Signal Processors (RASSP) is a new ARPA/Tri-Service initiative intended to dramatically improve the process by which complex digital systems, particularly embedded digital signal processors, are designed, manufactured, upgraded and supported. RASSP seeks to improve by at least a factor of four the time required to take a design from concept to fielded prototype. RASSP is motivated by the need to provide affordable embedded signal processors for a wide range of DoD systems that are state-of-the-art when they are fielded, rather than when they are first defined. This paper introduces the program from two viewpoints. The first is technical, covering the major concepts upon which the RASSP approach to design is based. The second is programmatic, covering the roles of the program participants and the program status as of this writing.<>
{"title":"The Rapid Prototyping of Application Specific Signal Processors (RASSP) program: overview and status","authors":"M. Richards","doi":"10.1109/IWRSP.1994.315915","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315915","url":null,"abstract":"The Rapid Prototyping of Application Specific Signal Processors (RASSP) is a new ARPA/Tri-Service initiative intended to dramatically improve the process by which complex digital systems, particularly embedded digital signal processors, are designed, manufactured, upgraded and supported. RASSP seeks to improve by at least a factor of four the time required to take a design from concept to fielded prototype. RASSP is motivated by the need to provide affordable embedded signal processors for a wide range of DoD systems that are state-of-the-art when they are fielded, rather than when they are first defined. This paper introduces the program from two viewpoints. The first is technical, covering the major concepts upon which the RASSP approach to design is based. The second is programmatic, covering the roles of the program participants and the program status as of this writing.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130911813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315903
W. Y. Lo, O. Choy, C. Chan
Describes a hardware emulation board based on field programmable gate arrays (FPGAs) and programmable interconnect switches to overcome the limitations of traditional verifications for ASIC designs. Both hardwired buses and programmable buses, via switches, contribute to the interconnection between the FPGAs. With a microprocessor and two EPROMs, the board is designed so that the microprocessor itself can be a part of emulation, in addition to downloading configuration data and testing. Finally presented is the software tool tailored to this board. It automatically partitions the design among multiple FPGAs, programs the switches and facilitates the design and verification process.<>
{"title":"Hardware emulation board based on FPGAs and programmable interconnections","authors":"W. Y. Lo, O. Choy, C. Chan","doi":"10.1109/IWRSP.1994.315903","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315903","url":null,"abstract":"Describes a hardware emulation board based on field programmable gate arrays (FPGAs) and programmable interconnect switches to overcome the limitations of traditional verifications for ASIC designs. Both hardwired buses and programmable buses, via switches, contribute to the interconnection between the FPGAs. With a microprocessor and two EPROMs, the board is designed so that the microprocessor itself can be a part of emulation, in addition to downloading configuration data and testing. Finally presented is the software tool tailored to this board. It automatically partitions the design among multiple FPGAs, programs the switches and facilitates the design and verification process.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122341542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315910
G. Azevedo, Helio Azevedo, M. Jino
Real time systems is an application area where digital computer usage has grown significantly in the last decade. It has done so in parallel with the development of techniques and the proposition of software engineering approaches aiming at an effective and economical way of producing software. Real time applications present features distinct from other applications and impose suitable techniques and models for software development. One of the most well-known methodologies, "Structured Development for Real-time Systems", by Ward and Mellor (1985), was used as the model for prototype generation in a real-time prototyping system (ProTR); ProTR is described and its application is shown through an example.<>
{"title":"ProTR: a tool for real-time systems development","authors":"G. Azevedo, Helio Azevedo, M. Jino","doi":"10.1109/IWRSP.1994.315910","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315910","url":null,"abstract":"Real time systems is an application area where digital computer usage has grown significantly in the last decade. It has done so in parallel with the development of techniques and the proposition of software engineering approaches aiming at an effective and economical way of producing software. Real time applications present features distinct from other applications and impose suitable techniques and models for software development. One of the most well-known methodologies, \"Structured Development for Real-time Systems\", by Ward and Mellor (1985), was used as the model for prototype generation in a real-time prototyping system (ProTR); ProTR is described and its application is shown through an example.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115503990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-21DOI: 10.1109/IWRSP.1994.315901
M. Courtoy
Logic emulation systems based on FPGAs are becoming a widely accepted solution for the verification of large, complex designs. However, the acceptance of this technology is still lagging for the verification of ASIC designs with 50,000 gates or less of custom logic. This paper presents Project Spinnaker, a project aimed at the development of a rapid prototyping solution for this market segment. The project emphasizes what are believed to be the three key aspects for broadening the acceptance of the emulation verification methodology among ASIC designers: speed, cost, and automation.<>
{"title":"Project Spinnaker: a new generation of rapid prototyping system","authors":"M. Courtoy","doi":"10.1109/IWRSP.1994.315901","DOIUrl":"https://doi.org/10.1109/IWRSP.1994.315901","url":null,"abstract":"Logic emulation systems based on FPGAs are becoming a widely accepted solution for the verification of large, complex designs. However, the acceptance of this technology is still lagging for the verification of ASIC designs with 50,000 gates or less of custom logic. This paper presents Project Spinnaker, a project aimed at the development of a rapid prototyping solution for this market segment. The project emphasizes what are believed to be the three key aspects for broadening the acceptance of the emulation verification methodology among ASIC designers: speed, cost, and automation.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123535458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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