{"title":"基于Artix-7 FPGA的低功耗SRAM设计","authors":"Tarun Agrawal, Anjan Kumar, S. K. Saraswat","doi":"10.1109/CCINTELS.2016.7878231","DOIUrl":null,"url":null,"abstract":"SRAM is associated with cache memory inside computer system, it increases overall speed of the system. In this work 64kb SRAM is synthesized and simulated on Artix-7 FPGA board by using different Input-Output Standard techniques. For designing SRAM, HSTL_I, HSTL_I_18, HSTL_II and HSTL_II_18 IO Standards are used and power dissipation is calculated on various range of operating frequencies and find HSTL_I is most power efficient IO Standard among these other IO Standards. at 1GHz, 2GHz and 3GHz operating frequency if HSTL_I is used in place of HSTL_II_18, 26.38%, 17.18% and 11.12% power can be saved.","PeriodicalId":158982,"journal":{"name":"2016 2nd International Conference on Communication Control and Intelligent Systems (CCIS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Design of low power SRAM on Artix-7 FPGA\",\"authors\":\"Tarun Agrawal, Anjan Kumar, S. K. Saraswat\",\"doi\":\"10.1109/CCINTELS.2016.7878231\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"SRAM is associated with cache memory inside computer system, it increases overall speed of the system. In this work 64kb SRAM is synthesized and simulated on Artix-7 FPGA board by using different Input-Output Standard techniques. For designing SRAM, HSTL_I, HSTL_I_18, HSTL_II and HSTL_II_18 IO Standards are used and power dissipation is calculated on various range of operating frequencies and find HSTL_I is most power efficient IO Standard among these other IO Standards. at 1GHz, 2GHz and 3GHz operating frequency if HSTL_I is used in place of HSTL_II_18, 26.38%, 17.18% and 11.12% power can be saved.\",\"PeriodicalId\":158982,\"journal\":{\"name\":\"2016 2nd International Conference on Communication Control and Intelligent Systems (CCIS)\",\"volume\":\"60 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 2nd International Conference on Communication Control and Intelligent Systems (CCIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCINTELS.2016.7878231\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 2nd International Conference on Communication Control and Intelligent Systems (CCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCINTELS.2016.7878231","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SRAM is associated with cache memory inside computer system, it increases overall speed of the system. In this work 64kb SRAM is synthesized and simulated on Artix-7 FPGA board by using different Input-Output Standard techniques. For designing SRAM, HSTL_I, HSTL_I_18, HSTL_II and HSTL_II_18 IO Standards are used and power dissipation is calculated on various range of operating frequencies and find HSTL_I is most power efficient IO Standard among these other IO Standards. at 1GHz, 2GHz and 3GHz operating frequency if HSTL_I is used in place of HSTL_II_18, 26.38%, 17.18% and 11.12% power can be saved.
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