{"title":"带隙启动电路FIB失效分析及改进","authors":"Qu Ruoyuan, Sun Jiajia, Z. Wei, Gong Xin","doi":"10.1109/IPFA.2018.8452593","DOIUrl":null,"url":null,"abstract":"Based on a failure analysis case of abnormal operating current of an ADC (Analog to Digital Convertor) chip, a step-by-step fault location method is introduced in this paper. The fault is located using this method, and FIB (focused ion beam) technology is involved to verify the accuracy of fault location. Meanwhile, another simulations verification method is adopted, which reveals that the failure reason lies in the reduction of the core capacitance in bandgap start-up circuit caused by inconsistencies of the process. At last, some suggestions are proposed to help fast location in the similar failure and to ensure that this risk can be effectively avoid in the future relevant design.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Failure Analysis and Improvement of Bandgap Start-up Circuit by FIB\",\"authors\":\"Qu Ruoyuan, Sun Jiajia, Z. Wei, Gong Xin\",\"doi\":\"10.1109/IPFA.2018.8452593\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Based on a failure analysis case of abnormal operating current of an ADC (Analog to Digital Convertor) chip, a step-by-step fault location method is introduced in this paper. The fault is located using this method, and FIB (focused ion beam) technology is involved to verify the accuracy of fault location. Meanwhile, another simulations verification method is adopted, which reveals that the failure reason lies in the reduction of the core capacitance in bandgap start-up circuit caused by inconsistencies of the process. At last, some suggestions are proposed to help fast location in the similar failure and to ensure that this risk can be effectively avoid in the future relevant design.\",\"PeriodicalId\":382811,\"journal\":{\"name\":\"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"volume\":\"82 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2018.8452593\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2018.8452593","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Failure Analysis and Improvement of Bandgap Start-up Circuit by FIB
Based on a failure analysis case of abnormal operating current of an ADC (Analog to Digital Convertor) chip, a step-by-step fault location method is introduced in this paper. The fault is located using this method, and FIB (focused ion beam) technology is involved to verify the accuracy of fault location. Meanwhile, another simulations verification method is adopted, which reveals that the failure reason lies in the reduction of the core capacitance in bandgap start-up circuit caused by inconsistencies of the process. At last, some suggestions are proposed to help fast location in the similar failure and to ensure that this risk can be effectively avoid in the future relevant design.