M. Matteis, A. Donno, Stefano Marinaci, S. D’Amico, A. Baschirotto
{"title":"一种采用28nm cmos芯片的0.9V三阶单opamp模拟滤波器","authors":"M. Matteis, A. Donno, Stefano Marinaci, S. D’Amico, A. Baschirotto","doi":"10.1109/IWASI.2017.7974237","DOIUrl":null,"url":null,"abstract":"A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μ\\ν without that the Signal-to-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 0.9V 3rd-order single-OPAMP analog filter in 28nm CMOS-bulk\",\"authors\":\"M. Matteis, A. Donno, Stefano Marinaci, S. D’Amico, A. Baschirotto\",\"doi\":\"10.1109/IWASI.2017.7974237\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μ\\\\ν without that the Signal-to-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.\",\"PeriodicalId\":332606,\"journal\":{\"name\":\"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWASI.2017.7974237\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWASI.2017.7974237","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.9V 3rd-order single-OPAMP analog filter in 28nm CMOS-bulk
A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μ\ν without that the Signal-to-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.