{"title":"采用0.35 /spl mu/m CMOS技术的4 GHz双模分频32/33预分频器","authors":"Fernando P. H. de Miranda, J. Navarro, W. Noije","doi":"10.1145/1016568.1016598","DOIUrl":null,"url":null,"abstract":"The design of a dual modulus prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called extended true single phase clock (E-TSPC), an extension of the true single phase clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 /spl mu/m CMOS technology\",\"authors\":\"Fernando P. H. de Miranda, J. Navarro, W. Noije\",\"doi\":\"10.1145/1016568.1016598\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a dual modulus prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called extended true single phase clock (E-TSPC), an extension of the true single phase clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.\",\"PeriodicalId\":275811,\"journal\":{\"name\":\"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1016568.1016598\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1016568.1016598","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 /spl mu/m CMOS technology
The design of a dual modulus prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called extended true single phase clock (E-TSPC), an extension of the true single phase clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.
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