An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors

The research presented in this paper details a number of further novel developments to a methodology known as “Pair and Swap”. Pair and Swap is a processor-level fault tolerance technique that enables graceful degradation in multi-core chips. The new developments are based around the introduction of a, hardware-based, decision unit into the system. The decision unit is a dependable solution to the problem of being able to reliably compare the comparison results of a pair of cores based on the current core pairings. The decision unit is determined to be more reliable, and efficient, than the cores due to the architectural simplicity it uses to perform the comparison, which is used to update eachcore’s configuration table. This paper will detail the complete decision unit implementation within the pair and swap methodology and show its ability to detect and gracefully degrade from both transient and permanent faults.