This paper proposes two efficient software techniques, Control-flow and Data Errors Correction using Data-flow Graph Consideration (CDCC) and Miniaturized Check-Pointing (MCP), to detect and correct control-flow errors. These techniques have been implemented based on addition of redundant codes in a given program. The creativity applied in the methods for online detection and correction of the control-flow errors is using data-flow graph alongside of using control-flow graph. These techniques can detect most of the control-flow errors in the program firstly, and next can correct them, automatically. Therefore, both errors in the control-flow and program data which is caused by control-flow errors can be corrected, efficiently. In order to evaluate the proposed techniques, a post compiler is used, so that the techniques can be applied to every 80X86 binaries, transparently. Three benchmarks quick sort, matrix multiplication and linked list are used, and a total of 5000 transient faults are injected on several executable points in each program. The experimental results demonstrate that at least 93% and 89% of the control-flow errors can be detected and corrected without any data error generation by the CDCC and MCP, respectively. Moreover, the strength of these techniques is significant reduction in the performance and memory overheads in compare to traditional methods, for as much as remarkable correction abilities.
{"title":"Two Efficient Software Techniques to Detect and Correct Control-Flow Errors","authors":"H. Zarandi, M. Maghsoudloo, N. Khoshavi","doi":"10.1109/PRDC.2010.10","DOIUrl":"https://doi.org/10.1109/PRDC.2010.10","url":null,"abstract":"This paper proposes two efficient software techniques, Control-flow and Data Errors Correction using Data-flow Graph Consideration (CDCC) and Miniaturized Check-Pointing (MCP), to detect and correct control-flow errors. These techniques have been implemented based on addition of redundant codes in a given program. The creativity applied in the methods for online detection and correction of the control-flow errors is using data-flow graph alongside of using control-flow graph. These techniques can detect most of the control-flow errors in the program firstly, and next can correct them, automatically. Therefore, both errors in the control-flow and program data which is caused by control-flow errors can be corrected, efficiently. In order to evaluate the proposed techniques, a post compiler is used, so that the techniques can be applied to every 80X86 binaries, transparently. Three benchmarks quick sort, matrix multiplication and linked list are used, and a total of 5000 transient faults are injected on several executable points in each program. The experimental results demonstrate that at least 93% and 89% of the control-flow errors can be detected and corrected without any data error generation by the CDCC and MCP, respectively. Moreover, the strength of these techniques is significant reduction in the performance and memory overheads in compare to traditional methods, for as much as remarkable correction abilities.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125155519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Existing redundant multithreading (RMT) detects faults by comparing the result of each instruction between the master and slave threads, which can lead to huge comparison and communication overhead. To address this problem, the checkpoint-based RMT (like RVQ_F) was proposed, but in such architectures, master threads must wait for slave threads to arrive at the same position at each checkpoint, this may delay the release of resources occupied by master threads and decrease performance. This paper proposes an asynchronous checkpoint-based redundant multithreading architecture (AC-RMT), in which two context saving rooms are set aside for each thread, one for detecting faults, and the other for saving the last checkpoint used for fault restoration. Compared with RVQ_F, AC-RMT efficiently boosts performance because, by avoiding the waiting of master threads at checkpoints, resources can be released timely.
{"title":"An Asynchronous Checkpoint-Based Redundant Multithreading Architecture","authors":"Jie Yin, Jianhui Jiang","doi":"10.1109/PRDC.2010.27","DOIUrl":"https://doi.org/10.1109/PRDC.2010.27","url":null,"abstract":"Existing redundant multithreading (RMT) detects faults by comparing the result of each instruction between the master and slave threads, which can lead to huge comparison and communication overhead. To address this problem, the checkpoint-based RMT (like RVQ_F) was proposed, but in such architectures, master threads must wait for slave threads to arrive at the same position at each checkpoint, this may delay the release of resources occupied by master threads and decrease performance. This paper proposes an asynchronous checkpoint-based redundant multithreading architecture (AC-RMT), in which two context saving rooms are set aside for each thread, one for detecting faults, and the other for saving the last checkpoint used for fault restoration. Compared with RVQ_F, AC-RMT efficiently boosts performance because, by avoiding the waiting of master threads at checkpoints, resources can be released timely.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122507031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This research aims to develop a formal framework for (1) formal validation for satisfiability of specifications to requirements, and (2) requirements management based on the Jackson's reference model for requirements and specifications, which provides an insight and perspective basis for relationship between requirements and specifications. To develop the framework, we use propositional logic, from which we derive formal discussion and devices for computer assistance. In the framework the validation for satisfiability of specifications to requirements is ascribed to the validity checking of logical formulas. Also within the framework we develop a useful notion of ``weakest adequate specifications'' with its calculating technique. We will demonstrate the usefulness of the framework with practical examples.
{"title":"Formal Validation and Requirements Management Based on the Jackson's Reference Model for Requirements and Specifications","authors":"Takashi Kitamura, Keishi Okamoto, M. Takeyama","doi":"10.1109/PRDC.2010.42","DOIUrl":"https://doi.org/10.1109/PRDC.2010.42","url":null,"abstract":"This research aims to develop a formal framework for (1) formal validation for satisfiability of specifications to requirements, and (2) requirements management based on the Jackson's reference model for requirements and specifications, which provides an insight and perspective basis for relationship between requirements and specifications. To develop the framework, we use propositional logic, from which we derive formal discussion and devices for computer assistance. In the framework the validation for satisfiability of specifications to requirements is ascribed to the validity checking of logical formulas. Also within the framework we develop a useful notion of ``weakest adequate specifications'' with its calculating technique. We will demonstrate the usefulness of the framework with practical examples.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122525627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Y. Nakashima, Kazutoshi Kobayashi
In this paper, we proposed a light-weighted recovery scheme for fault tolerable pipeline processors after error has been detected by redundant executions. A minimal rolling back procedure is designed to schedule the re-execution based recovery in a one-cycle delay. This scheme makes full use of in-fly pipeline working status to aid the recovery, which relieves the recovery from a large checkpoint buffer.
{"title":"A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors","authors":"Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Y. Nakashima, Kazutoshi Kobayashi","doi":"10.1109/PRDC.2010.44","DOIUrl":"https://doi.org/10.1109/PRDC.2010.44","url":null,"abstract":"In this paper, we proposed a light-weighted recovery scheme for fault tolerable pipeline processors after error has been detected by redundant executions. A minimal rolling back procedure is designed to schedule the re-execution based recovery in a one-cycle delay. This scheme makes full use of in-fly pipeline working status to aid the recovery, which relieves the recovery from a large checkpoint buffer.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122009459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Virtual machine monitors (VMMs) have emerged as potential tools %% are one of the promising approaches for implementing security mechanisms to enhance the security and/or reliability of software systems. There are two approaches to implementing VMMs. One is a software-based approach that emulates the execution of virtual machines via software. The other is a hardware-based approach that utilizes the hardware virtualization support of CPUs. The software-based approach is preferred for implementing security mechanisms, whereas the hardware-based approach is preferred from the viewpoint of performance. In this paper, we present an approach to implementing a hybrid VMM for flexible and efficient security mechanisms. The hybrid VMM consists of a software-based VMM (QEMU) and hardware-based VMM (KVM), and it dynamically switches between them. Using the hybrid VMM, security- and reliability-critical software can be executed on the software-based VMM, and performance-critical software can be executed on the hardware-based VMM. We also present the results of experiments conducted to evaluate the performance and verify the effectiveness of the hybrid VMM.
{"title":"Implementing a Hybrid Virtual Machine Monitor for Flexible and Efficient Security Mechanisms","authors":"Junya Sawazaki, T. Maeda, A. Yonezawa","doi":"10.1109/PRDC.2010.32","DOIUrl":"https://doi.org/10.1109/PRDC.2010.32","url":null,"abstract":"Virtual machine monitors (VMMs) have emerged as potential tools %% are one of the promising approaches for implementing security mechanisms to enhance the security and/or reliability of software systems. There are two approaches to implementing VMMs. One is a software-based approach that emulates the execution of virtual machines via software. The other is a hardware-based approach that utilizes the hardware virtualization support of CPUs. The software-based approach is preferred for implementing security mechanisms, whereas the hardware-based approach is preferred from the viewpoint of performance. In this paper, we present an approach to implementing a hybrid VMM for flexible and efficient security mechanisms. The hybrid VMM consists of a software-based VMM (QEMU) and hardware-based VMM (KVM), and it dynamically switches between them. Using the hybrid VMM, security- and reliability-critical software can be executed on the software-based VMM, and performance-critical software can be executed on the hardware-based VMM. We also present the results of experiments conducted to evaluate the performance and verify the effectiveness of the hybrid VMM.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129160665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems. For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. Especially, quantitative metric of integrity has not been proposed yet. This paper proposes quantitative metric for integrity for remote systems based on the Internet. It is also useful for evaluation of the effect of the measure against data destruction elements. This paper applies it to example systems in order to confirm its effectiveness.
{"title":"Quantitative Evaluation of Integrity for Remote System Using the Internet","authors":"M. Kitakami, Hiroshi Konno, K. Namba, Hideo Ito","doi":"10.1109/PRDC.2010.13","DOIUrl":"https://doi.org/10.1109/PRDC.2010.13","url":null,"abstract":"Recently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems. For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. Especially, quantitative metric of integrity has not been proposed yet. This paper proposes quantitative metric for integrity for remote systems based on the Internet. It is also useful for evaluation of the effect of the measure against data destruction elements. This paper applies it to example systems in order to confirm its effectiveness.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133618124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a new safe measurement-based estimation method for Worst-Case Execution Time (WCET) of programs in real-time systems. The latest progress in Pattern Recognition of learning to detect unseen object classes by between-class attribute transfer has been used for automatic test-data generation in our method. Based on control flow graph partition, execution profiles of each basic block and probabilities of their executions can be extracted during program executions driven by test data. Afterwards, a critical path can be identified by calculating its execution probability among all feasible paths. With measurement for critical paths, WCET can be obtained by adding static analysis of hardware features to measurement results. The objective of this paper is not to present finished or almost finished work. Instead we hope to trigger discussion and solicit feedback from the community in order to avoid pitfalls experienced by others and to help focus our research.
{"title":"A Safe Measurement-Based Worst-Case Execution Time Estimation Using Automatic Test-Data Generation","authors":"L. Kong, Jianhui Jiang","doi":"10.1109/PRDC.2010.28","DOIUrl":"https://doi.org/10.1109/PRDC.2010.28","url":null,"abstract":"This paper proposes a new safe measurement-based estimation method for Worst-Case Execution Time (WCET) of programs in real-time systems. The latest progress in Pattern Recognition of learning to detect unseen object classes by between-class attribute transfer has been used for automatic test-data generation in our method. Based on control flow graph partition, execution profiles of each basic block and probabilities of their executions can be extracted during program executions driven by test data. Afterwards, a critical path can be identified by calculating its execution probability among all feasible paths. With measurement for critical paths, WCET can be obtained by adding static analysis of hardware features to measurement results. The objective of this paper is not to present finished or almost finished work. Instead we hope to trigger discussion and solicit feedback from the community in order to avoid pitfalls experienced by others and to help focus our research.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114333391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Kinebuchi, T. Nakajima, V. Ganapathy, L. Iftode
This paper proposes a method for protecting data by leveraging core-local memory. Core-local (or software coherency managed) memory is a programmable memory which is equipped in a core of multicore processors. It is accessible from the core with low latency compared to a shared cache and a shared main memory. This is equipped in multicore processors in order to exploit locality of threads and to improve scalability. In addition to low latency, core-local memory is invisible and inaccessible from the other cores. We leverage this characteristic to provide a novel mechanism of protecting an OS kernel beside MMU based address space separation.
{"title":"Core-Local Memory Assisted Protection","authors":"Y. Kinebuchi, T. Nakajima, V. Ganapathy, L. Iftode","doi":"10.1109/PRDC.2010.48","DOIUrl":"https://doi.org/10.1109/PRDC.2010.48","url":null,"abstract":"This paper proposes a method for protecting data by leveraging core-local memory. Core-local (or software coherency managed) memory is a programmable memory which is equipped in a core of multicore processors. It is accessible from the core with low latency compared to a shared cache and a shared main memory. This is equipped in multicore processors in order to exploit locality of threads and to improve scalability. In addition to low latency, core-local memory is invisible and inaccessible from the other cores. We leverage this characteristic to provide a novel mechanism of protecting an OS kernel beside MMU based address space separation.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131664929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The research presented in this paper details a number of further novel developments to a methodology known as “Pair and Swap”. Pair and Swap is a processor-level fault tolerance technique that enables graceful degradation in multi-core chips. The new developments are based around the introduction of a, hardware-based, decision unit into the system. The decision unit is a dependable solution to the problem of being able to reliably compare the comparison results of a pair of cores based on the current core pairings. The decision unit is determined to be more reliable, and efficient, than the cores due to the architectural simplicity it uses to perform the comparison, which is used to update eachcore’s configuration table. This paper will detail the complete decision unit implementation within the pair and swap methodology and show its ability to detect and gracefully degrade from both transient and permanent faults.
{"title":"An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors","authors":"J. Weston, Masashi Imai, Tomohide Nagai, T. Nanya","doi":"10.1109/PRDC.2010.43","DOIUrl":"https://doi.org/10.1109/PRDC.2010.43","url":null,"abstract":"The research presented in this paper details a number of further novel developments to a methodology known as “Pair and Swap”. Pair and Swap is a processor-level fault tolerance technique that enables graceful degradation in multi-core chips. The new developments are based around the introduction of a, hardware-based, decision unit into the system. The decision unit is a dependable solution to the problem of being able to reliably compare the comparison results of a pair of cores based on the current core pairings. The decision unit is determined to be more reliable, and efficient, than the cores due to the architectural simplicity it uses to perform the comparison, which is used to update eachcore’s configuration table. This paper will detail the complete decision unit implementation within the pair and swap methodology and show its ability to detect and gracefully degrade from both transient and permanent faults.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124924744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Business critical applications are increasingly being deployed as web services that access database systems, and must provide secure operations to its clients. Although the open web environment emphasizes the need for security, several studies show that web services are still being deployed with command injection vulnerabilities. This paper proposes a learning-based approach to secure web services against SQL and XPath Injection attacks. Our approach is able to transparently learn valid request patterns (learning phase) and then detect and abort potentially harmful requests (protection phase). When it is not possible to have a complete learning phase, a set of heuristics can be used to accept/discard doubtful cases. Our mechanism was applied to secure TPC-App services and open source services. It showed to be extremely effective in stopping all tested attacks, while introducing a negligible performance impact.
{"title":"A Learning-Based Approach to Secure Web Services from SQL/XPath Injection Attacks","authors":"N. Laranjeiro, M. Vieira, H. Madeira","doi":"10.1109/PRDC.2010.24","DOIUrl":"https://doi.org/10.1109/PRDC.2010.24","url":null,"abstract":"Business critical applications are increasingly being deployed as web services that access database systems, and must provide secure operations to its clients. Although the open web environment emphasizes the need for security, several studies show that web services are still being deployed with command injection vulnerabilities. This paper proposes a learning-based approach to secure web services against SQL and XPath Injection attacks. Our approach is able to transparently learn valid request patterns (learning phase) and then detect and abort potentially harmful requests (protection phase). When it is not possible to have a complete learning phase, a set of heuristics can be used to accept/discard doubtful cases. Our mechanism was applied to secure TPC-App services and open source services. It showed to be extremely effective in stopping all tested attacks, while introducing a negligible performance impact.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115220624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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